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AFE58JD48: How to config JESD204B LMFS, K Parameters for 2 co-working AFE58JD48

Gaofeng Zhao
Prodigy 80 points
Part Number: AFE58JD48

Tool/software:

Hi TI experts,

I am planning to use one FPGA to communicate with two AFE58JD48 devices simultaneously. Both AFEs are working in 80x mode (4-lane mode). I would like to consider the two AFE58JD48 devices as a single 32-ADC, 8-lane JESD204B transmitter so that I can use an 8-lane JESD204B RX FPGA IP core to receive data from the two AFEs. Is this solution feasible?
I had assumed that this solution would work, but I am having trouble configuring the LMFS parameters. In the JESD 80X mode section of the AFE58JD48 documentation, it states, "Each 8-channel ADC die has separate JESD IPs. Hence, these parameters are derived considering the ADC as an 8-channel device." It also specifies that "L must be set to 2. M must be set to 8." It seems that I have to treat the two AFEs as four JESD transmitters and then use four JESD RX cores in the FPGA to accept the data. This approach creates a lot of difficulties in the FPGA and PCB design (e.g., doubled ~SYNC wiring). Can I ask for some advice on this?
  • 0
    TI__Expert 6965 points

    Hi,

    I will get back on this shortly .

  • 0
    Prodigy 80 points

    Hi Sachin,

    After browsing more information, I have thought more about this issue, before I said that the statement that the two AFE58JD48 are considered as a 32-ch/8-lane JESD transmitter should be wrong, these two AFE58JD48 (80x mode) should be received as four 8-ch/2-lane JESD transmitters.

    I still think I can use a Xilinx JESD204C IP core to handle these four JESD links, and only need to configure L/M/F=2/8/8 (80X) as per the AFE58JD48 documentation, since the JESD IP core maintains the rx ila data for each lane individually, is this right?

    Also, I have a question about your official AFE58JD48 JESD reference design, why only two lanes of the JESD rx core are activated in the code, when it is clear that in 40X mode (F=4) all lanes should be activated.

    Code location: JESD_TOP.v line34           parameter active_lanes = 72

  • 0 in reply to Gaofeng Zhao
    TI__Expert 6965 points

    Yes , By properly setting LMF parameter in FPGA you can handle this . This device supports JESD204B not JESD204C . 

    In this example it looks like there are receiving data in only 2 lanes .(lane _mode parameter) . So it might not the example for 40X mode . 

  • 0 in reply to Sachin H K
    Prodigy 80 points

    I had to use the Xilinx JESD204C IP core to be backward compatible with the JESD204B because the JESD204B IP core was deprecated in the vivado version after v2022.1 (and probably a bit earlier).

    I think the reference project is the 40x mode because of the use of 8 lanes of one AFE and the setting of F=4