AMC3336: AMC3336 DC-offset problem

Dear Alexander,

thanks for your quick response. The first document you send is something we encountered. We have FPGA sin3filter demodulator and send clock from FPGA and receive data at FPGA. But we have big delay between clock and data and we encountered time violation and thats why we lower the clock from 20Mhz to 10Mhz now it works fine, but we test also 12.5Mhz and we encountered something different I guess, because from the osciloscope it seems like the data from adc "skipping ones" you can see it on attached photos below. From our measurement and calculation at 12.5MHz there is no time hazard.
What I do i just unpluging and plugging connector between control PCB(theres FPGA and diff.lines+connector) and measurement PCB (connector+diff.lines+ADCs) and problem sometimes occure. It even happens at power up in our converter where we used these

Here you can see normal operation at 12.5Mhz(yellow=clock/green=data_from_adc):

Here is problem occured(yellow=clock/green=data_from_adc):

Just adding some info: When data error occur power on secondary side=3.48V and after LDO=3.21V and its the same voltage levels as in correct data operation. Shorting primary_power/secondary_power/clock to GND fix it (guess power-up restart). Its not latch-up but It certainly something with the CLK. Could it be some problem that CLK is logic HIGH during power up? Is it necessary to held CLK in low level during power-up by some pull down? I couldn find anything in datasheet for CLK pin, only just RC filter for trace impedance optimization. But it strange that it works on 20Mhz/15Mhz/10Mhz and not in 12.5Mhz.

Hi Tomas,

Applying the clock before low side (VDD2) power up violates the absolute maximum ratings of the device. Is this what you mean by secondary side? 

I mean when rising VDD voltage(orange) the clock pin voltage(blue) also rising with it to logic high and after some time the clock appear with first pulse going logic low (the signals are undersampled on osciloscope the pulses are real nice squares=ignore green/blue like noise on pics). Should I kept CLK low during power up? The clock pin is driven by diff. line IC SN65C1167E without default state on input (undefined output). I could try give pull up+pulldown on IN_P/IN_N pins so when power-up clock stays logic low. What do you think? Kind regards Thomas

Hi Thomas,

I would recommend keeping CLK low until DVDD has properly established. Any luck the last few days? 

Dear Alexander,

Even if I keep CLK low during power up it did not help. Sometimes the first clock from Diif.line.driver SN65C1167E seems not to keep duty cycle 50%/50% but starts at 38%/62% duty cycle and after few clock it stabilize to 48%/52% but looks like it do something to ADC and ADC then sending data with offset. I think I need to some impedance trace adjustment. Because One diff. line driver output feed four ADCs with clock on one trace. Do you suggest to have for every ADC some own clock driver and trace? Could it be something with the impedance trace adjustment with bad reflection?

Kind regards Thomas

Hi Tomas,

I am not a clocking expert, you may try posting another thread with this device to get into contact with the best support. 

However, if detailed management of the clock and data lines is not ideal, you may consider a driver/buffer to help stabilize the clock.