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ads62p45 vs ads62p49

Tyrel Newton
Prodigy 50 points
Other Parts Discussed in Thread: ADS62P45, ADS62P29, CDCE72010, LMK03806

I'm in the process of bringing up a board that currently has an ADS62P45 on it. The board was designed to support both the p45 and p49 families in a similar fashion to the EVM. I used the p49 as a reference for the board and we ultimately decided on the lower rate p45. Aside from the 1.8V vs. 3.3V power supply differences, there are a couple of extra differences:

- on the p45, pin 64 is DRGND while on the p49, pin 64 is SDOUT

- on the p45, pin 22 is AGND while on the p49, pin is listed as NC

Because I used the p49 as a reference, I left pin 22 as an NC and routed pin 64 as a trace to an FPGA.

As I'm trying to bring up this board that now has a p45 on it, I'm having difficulty getting the CLKOUT signal to produce anything useful (in both LVDS and CMOS modes). Basically, the CLKOUT only works (in either mode) at pretty low frequencies (i.e. it looks OK at 10 MHz). At higher frequencies, the CLKOUT doesn't seem to have enough drive strength to drive away from the center voltage. On a scope, it basically looks like very low amplitude overshoot and ringing. At 10 MHz, the CLKOUT looks reasonably OK in either LVDS or CMOS modes. In contrast, the data lines look significantly better at the max frequency (125 MHz) in both LVDS and CMOS modes.

Both the CLKOUT and DATA lines are routed directly to a Xilinx FPGA with the CLKOUT going into a GCLK pin. All routes are length matched to the FPGA and are routed as differential pairs for LVDS mode, even though I'm trying to test at the moment in CMOS mode.

I have tried adjusting the various drive strength and internal termination settings to no avail. But given that the DATA lines looks so much better with the default CMOS drive settings, I'm inclined to think its not a settings problem.

The only thing I can think of at this point is that since I didn't connect pin 64 to DRGND, maybe this is an important supply pin for the CLKOUT drive circuitry. On a scope, the voltage on the pin reads as 0V even though its terminated as an input into the FPGA.

Any help and/or insight would be much appreciated. Thanks!

  • 0
    TI__Genius 17370 points

    Hi Tyrel,

    Is it possible for you to cut the trace and use a wire to jumper DRGND over to this pin? That should tell you about the importance of the pin. I can check with the design team, but it will have to wait until after the holiday.

    Can you make sure there is not an excessive load on the CLKOUT pin? For instance, make sure that the GCLK pin is not set as an output such that it is trying to drive the line in one direction while the CLKOUT pins are trying to drive it the other way.

    A schematic and layout could also help with this.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Prodigy 50 points

    Matt,

    After posting, I did try jumpering both pin 64 and pin 22 (AGND) to ground while monitoring the clock output. No change. I have also verified that the configuration of the GCLK pin to be an input.

    I should also point out I'm using the Spartan-3A DSP 1800 development board and the ADC is on a daugtherboard that is connected to the FPGA development board through the EXP connectors provided (Samtec QSE/QTE). It may be that these high-density connectors are adding significant load capacitance to the CLKOUT signal. However, this is pretty much the same configuration used on the EVM. I suppose it may be that the EVM is incapable of operating in CMOS mode because of this, but I don't know that for sure.

    I'll post the design files if all else fails. But the schematic is pretty simple, the CLKOUT and DATA lines go straight to the FPGA. All LVDS pairs are routed on an inner layer to the EXP (Samtec QSE) connector. This route layer is sandwiched between a ground plane and a 3.3V power plane (both of which are unbroken across the board).

    I also can't rule out the fact that my scope and probe may be excessively loading the CLKOUT line. But again, the DATA lines look just fine using the same scope and probe.

    At the moment, I'm working on modifying the FPGA application to accept the DDR LVDS outputs of the ADC. Perhaps adding in the 100ohm termination at the FPGA inputs will help.

    Thanks,

    Tyrel

     

  • 0
    Prodigy 50 points

    UPDATE

    In lieu of using the CMOS output mode, I think I actually have the LVDS output mode working now. Previously, when I said the LVDS mode wasn't working, I wasn't using the 100ohm termination resistors in the FPGA because I was trying to get the CMOS mode to work. (I did have the internal termination resistors in the ADS62P45 turned on though.) Either way, switching to LVDS mode and correctly terminating at the FPGA  seems to work well for this design. The LVDS signals look good on a scope--at least at the driving end of the link.

    I did pick up a ADS62P45 EVM so that I can compare output characteristics between my board and the EVM. Hopefully, this will shed some light on why I could not get the CMOS mode to work.

     

  • 0 in reply to Matt Guibord
    Prodigy 120 points

    hi,Matt,

    I  am doing some evaluation on TI's ADS62P29 EVM board. Now I am confused about the CLK input ,Can you give some advice?

    Datasheet recommends three clk input option.

    option 1 is from the external functional generator, however I do not have this equipment which meets the requirements now.

    option 2 is from VCXO . I have to buy TCO-2111T@983.04MHZ and Toyocom's 245.76MHz Filter which I can't find it . It seems that these devices are TI customed ....How can I get it？

    option 3 is from VCXO without FLT and feedback. All I got is a 622.08MHz VCXO, I sold it in the EVM board . I want to know how can I check this crystal is running successfully?

    VCXO is PECL output , I can not use a oscilloscope to probe pin. 

    THANK YOU very much.

    ALAN

  • 0 in reply to ting wang93586
    TI__Genius 17370 points

    Alan,

    I'm not entirely sure about the CDCE72010 on this board. I've never used it. I believe you'll need some way to send SPI signals to the CDCE chip for programming. A better option may be to get a dedicated clocking board, either the CDCE72010 or the LMK03806.

    Regards,
    Matt Guibord