Other Parts Discussed in Thread: TSW14DL3200EVM
Tool/software:
Hello,
We have connected the ADC12DL2500 to FPGA Ultrascale+ and use the same clocking as is on the EVM. We verified the digital interface using all kinds of UPAT patterns under different temperature, PLL clock settings and power supply Voltage loads. And the digital pattern is always loaded into the FPGA as expected. So it seems the digital interface from ADC to FPGA is stable.
When we only change ADC register 0x0205 from 0x11 to 0x02 going into analog pattern mode then we start seeing issues. It shows up as big spikes in the data. Seemingly caused by a delayed capture of an LVDS bit causing a digital bit flip. We tried 2.5Gsps and 1.0Gsps, but the issue remains.
We verified the FPGA extensively and think the FPGA is working ok. So we suspect it comes out of the ADC when going into analog mode.
Is there anything else we can try to fix this issue?
Kind regards!
