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DAC70501: SPI communication problem - DAC OUTPUT Register

Marko Aksentijevic
Prodigy 20 points
Part Number: DAC70501
Other Parts Discussed in Thread: DAC80501, DAC60501

Tool/software:

Hello!

I am using DAC70501MDGSR and I am trying to set-up registers by writing into them via SPI protocol (1 MHz clock).

I am using internal reference (VREFIO = 2.5V). SPI2C pin is tied to GND. With this code I am trying to make DAC output = 1.25V. However, nothing is happening - DAC output stays at 2.5V! Also, when I try different values. DAC output voltage is not changing!

//SPI: PC0 - CS, PC1 - SDIN/SDA, PC2 - SCLK

//SYNC
PC0::clear();
USART<0>::TXDATA<>() = 0b0000'0010;
USART<0>::TXDATA<>() = 0b0000'0000;
USART<0>::TXDATA<>() = 0b0000'0000;
PC0::set();

//CONFIG
PC0::clear();
USART<0>::TXDATA<>() = 0b0000'0011;
USART<0>::TXDATA<>() = 0b0000'0000;
USART<0>::TXDATA<>() = 0b0000'0000;
PC0::set();

//GAIN
PC0::clear();
USART<0>::TXDATA<>() = 0b0000'0100;
USART<0>::TXDATA<>() = 0b0000'0000;
USART<0>::TXDATA<>() = 0b0000'0000;
PC0::set();

//TRIGGER
PC0::clear();
USART<0>::TXDATA<>() = 0b0000'0101;
USART<0>::TXDATA<>() = 0b0000'0000;
USART<0>::TXDATA<>() = 0b0000'0000;
PC0::set();

//DAC DATA
PC0::clear();
USART<0>::TXDATA<>() = 0b0000'1000;
USART<0>::TXDATA<>() = 0b0010'0000;
USART<0>::TXDATA<>() = 0b0000'0000;
PC0::set();

Here are my oscillograms:

I checked table 7.6 Timing Requirements: SPI Mode table and Figure 7-1. SPI Mode Timing (from DACx0501 datasheet), but everything seems good to me!

Could you please help identify what I might be overlooking or any mistake I may have made?

Best regards,
Marko Aksentijević

  • 0
    Prodigy 20 points

    And just to check – DAC register for DAC70501 considers only last 13 bits, right?

    I find a little bit confusing this description from datasheet. I mean it is not 100% clear to me does it mean that it considers only last 13 bits or it considers [15:2] bits and last two bits are zero?

    Best regards,
    Marko

  • 0 in reply to Marko Aksentijevic
    TI__Mastermind 42273 points

    Hi Marko, 

    The DAC70501 is a 14-bit device, so the field width is [13:0], or 14 bits. The last two bits in the register are ignored. This is so all of the devices in the family will work with the same code. You can either treat the data like 16-bit (and the device ignores the lower two bits) or treat the data like 14-bit and shift it left by two before writing to the register. 

    For 1.25V you should write 0x4000 to the data register. 

    What is your VDD? And what are the logic levels of your SPI?

    Make sure you are using a SPI mode that shifts out data on the rising edge of SCLK because the DAC captures data on the falling edge. It looks like you are, but it is a bit hard to tell in the screenshot. 

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    Prodigy 20 points

    Hi Katlynne,

    First of all, thank you for your fast response!

    If I understood well that two last bits in DAC register are ignored, then, for me, that would be reasonable if in datasheet would be:

    DAC80501: DATA[15:0]
    DAC70501: DATA[15:2], 0, 0
    DAC60501: DATA[15:4], 0, 0, 0, 0

    instead of:

    DAC80501: DATA[15:0]
    DAC70501: DATA[13:0], 0, 0
    DAC60501: DATA[11:0], 0, 0, 0, 0

    As it stands now, I think it may be a little bit confusing.

    Then, if I am using internal reference (VREFIO = 2.5V), why for 1.25V I should write 0x4000 to the data register? I mean shouldn’t 0x8000 (0b1000’0000’0000’0000) be the correct value for 1.25V output? And for example if I want maximum possible value it should be then 0xFFFC (0b1111’1111’1111’1100), since two last bits are ignored?

    My VDD is 5V and logic high level of SPI signals is 3V.

    Yes, I am using SPI mode that shifts out data on the rising edge (CS - green, SDIN - orange, SCLK - yellow):

    Please correct me if I am wrong somewhere...

    Best regards,
    Marko

  • +1 in reply to Marko Aksentijevic
    TI__Mastermind 42273 points

    Hi Marko, 

    I should have noticed in your code that you were setting the gain bit to 0. I assumed you were using the 2x gain mode to get a 0 to 5V output, so 1.25 would be 0x4000. If you are using a 0 to 2.5V range (1x gain mode with VREF = 2.5V), then yes you are right, the data would be 0x8000. yes, 0xFFFC would be full scale (2.5V in the 0V to 2.5V range). 

    I expect that none of your commands are going through given that the output is still at the reset value of 2.5V (mid-scale in 0V to 5V default range). 3V SPI should be fine as our input logic levels are not dependent on VDD. Can you add a capacitor near the DAC on SCLK to try and filter those spikes on the rising and falling edges? 

    Best,

    Katlynne Jones 

  • 0 in reply to Katlynne Jones
    Prodigy 20 points

    Hi Katlynne,

    I misconfigured pinout and it was the main reason why SPI communication didn’t work...

    Nevertheless, your advise was very useful – 100pF capacitor perfectly filtered SCLK signal spikes!

    Once again, thank you for your time and willingness to help resolve my problem.

    Best regards,
    Marko

  • 0 in reply to Marko Aksentijevic
    TI__Mastermind 42273 points

    Hi Marko, 

    That is great to hear. Let me know if you run into any more trouble. 

    Best,

    Katlynne Jones