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ADC088S022: Regarding the high-speed SPI design issues of ADC088S022.

SHENG YANG
Expert 1270 points
Part Number: ADC088S022
Other Parts Discussed in Thread: ADC088S102

Tool/software:

ALL HI

As shown in the diagram, if SCLK is designed at 10 MHz, does TI have any relevant guidelines for high‑speed SPI circuit design? For instance, are there design recommendations regarding trace lengths, impedance matching, PCB layout, EMC, etc.? Thank you.

  • 0
    TI__Genius 10465 points

    Hi Sheng,

    This device is specified up to 200ksps at a 3.2MHz SCLK frequency, so I can't guarantee performance above that SCLK frequency. The datasheet formatting makes this a bit confusing, but that would be the limit on this device. If you would like to use up to a 16MHz SCLK, the ADC088S102 is the 1MSPS version of this device.

    I don't believe we have a specific document detailing the above considerations with SPI. At a 10MHz SCLK, you still have good design flexibility while maintaining signal integrity and EMC. Some general considerations are below. With SPI, there aren't any specific trace impedances you need to design for, as long as they are all similar.

    1. Keep traces short and direct (no 90 degree turns)
    2. Add small value series resistance to slow down rise times and to reduce ringing/overshoots
    3. Run SPI lines over ground plane or ground pour

    Usually these guidelines are enough to not require more rigorous analysis. 

    For deeper discussion on EMC, I suggest watching our TI Precision Labs series on ADCs, specifically the "PCB design for good EMC" videos.

    Regards,
    Joel

  • 0 in reply to Joel Meraz
    Expert 1270 points

    HI Joel Meraz 

    Thank you for your reply. I understand that some ADC products from ADI, which have 16 channels, can achieve SPI speeds of up to 40–50 MHz. I would like to know if TI has similar products. If SPI using such a clock frequency is employed, should additional anti‐interference design measures be considered in hardware design?

  • +1 in reply to SHENG YANG
    TI__Genius 10465 points

    Hi Sheng,

    It would be helpful to understand your use case a little bit more, and what requirements you need, since the maximum sampling rate generally correlates to the maximum SPI SCLK frequency. Even at 40-50MHz, the general guidelines remain the same, but should be abided by more strictly. It isn't necessarily required to design with anti-interference measures in mind.

    1. How many channels do you require?

    2. What sampling rate do you need for each channel, and what is the total sampling rate you will need across all channels?

    3. What resolution do you require?

    4. Are there any other special features you require from the ADC?

    Regards,
    Joel