ADC3910D065: Possible to configure SDR with DCLK being twice the frequency of sampling clock?

Elso

Part Number: ADC3910D065

Tool/software:

Hi,

I am designing a PCB using the ADC3910D065, but I am curious about the configuration possibilities. In the datasheet there is alot of examples using serialization with SDR and DDR etc, but not for the case I want to use. So I am wondering if this is possible:

I want to use SDR mode getting data from channel A and channel B, where the parallel bus has twice the clock frequency of the sampling clock. I got a little confused by the datasheet if this is possible?
I am using it with an Parallel Synchronous Slave Interface (PSSI) or Digital Camera Interface (DCMI) on a STM32H723 MCU, trying to avoid using FPGA.

I would appreciate some help!

6 months ago

+1 Luke Allen 6 months ago

TI__Intellectual 1370 points

Hello,

The mode you have described is DDR mode, except with a DCLK that is 2x the Sample clock. Unfortunately, the ADC does not have the ability to output a DCLK at a rate higher than the sample clock. To achieve what you have described, you would have to multiply the DCLK outside of the ADC.

Best,

Luke Allen

0 Elso 6 months ago in reply to Luke Allen

Prodigy 10 points

My problem is that the MCU only handles either falling or rising edge, and not both.

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ADC3910D065: Possible to configure SDR with DCLK being twice the frequency of sampling clock?