ADS131B04-Q1: Offset difference between power modes

Hi Dries Kooistra,

This is related to your circuit in front of the ADC. I do not know what your circuit is and where you shorted, but one possible reason could be, you are using unbalanced resistors that generated an offset error when input current flowed through them. You can debug and check it by moving the position of the short point.

BR,

Dale

The short point was close to the ADS131B04-Q1 channel 1 input pins. Differential input capacitor C563 in the below image was shorted.

NOTE: Input pins were shorted only to each other by this. They were not shorted to AGND too, like what the MUX 0x01 setting does.

Hi Dries Kooistra,

There is a difference between your external input short and internal input short. You only short both AINxP and AINxN pins externally. However, when the MUX[1:0] is set to 0x01, both AINxP and AINxN pins are internally shorted together and also they are tied to the AGND of the ADC, see the following simplified input circuit from ADS131B04-Q1 datasheet. You can try to short both pins to the ground of your circuit board, you should be able to see a similar result.

BR,

Dale

Hi Dale,

Thank you for your quick reply.

I know that the MUX setting 0x01 also connects both inputs to to AGND. I mentioned it in the last line of the previous post as a difference to what was done on the printed circuit board.

Because the MUX also connects to AGND, the setting the MUX to 0x01 cannot be used to determine the measurement offset error for a differential measurement. Please, correct me if I'm wrong. A better measurement offset error determination, used to correct measurement offset error for a differential measurement, would be to short the ADS131 input pins externally without connecting these to AGND.

The way I understand the offset error (input referred) as listed in the Electrical Specifications is that this is the expected error when only the input pins are shorted, and not shorted to AGND too.

I know the ±0.4 µV input referred offset error is 'typical' and that this is one sigma deviation from the mean. So the observed offset is regarded to be within specification. What is remarkable that all of the ADS131B04-Q1 that we've tested so far show a mean of  ADC readings between -16 µV and -19 µV. (or +16 µV and +19 µV, depending on the polarity) This got me puzzled as I would have expected more random results within the typical offset error specification. i.e. a mean of readings between +20 and -20 µV. Is this what could be expected?

I also did not expect such a difference in offset error between power modes. Offset error difference between channels and gain selection are presented quite clearly for the high resolution power mode in the datasheet (Typical characteristics in figures 6-4 to 6-7) but I cannot seem to find any mentioning of offset error difference between different power modes. Based on our test results it looks like the low power mode has much better offset error specifications than the high resolution power mode and the very low power mode. Is this what could be expected?

Kind regards,

Dries

EDIT 2025-04-24:

NOTE: The above values are internal on the ADC input, thus after programmable gain amplifier (PGA) and not on the ADS131B04 input pins. To get the 'input referred' value as stated in the specifications, the above values should be divided by 32.

Hi Dries,

Thanks for your clarification. 

For many ADCs that use a single and unipolar power supply for differential input, both positive and negative input pins should be shorted together at mid-power supply to measure the offset error of the analog front-end and the ADC, ADS124S08 is one of the ADCs like this that is internally shorted to (AVDD+AVDD)/2. 

The ADS131B04-Q1 has an integrated negative charge pump that allows for input voltages below AGND with a unipolar power supply, so the input can be shorted to the AGND. Shorting the inputs internally that has been tied to AGND or externally is a simple way to check the input-referred offset.

I did a test on the ADS131B04-Q1EVM. As you can see the result from the table below, shorting the inputs to AGND internally or externally shows a similar result that matches the specification as well, however an external short not to the AGND shows a little higher offset error on some channels, but they still meet the min/max specification of the offset error.

I suggest you to do a similar test. If your calculation from code to voltage is correct and your measured offset error is much higher than what I measured on the EVM, that indicates that your circuit or PCB board design can be improved. The measured offset error should be close in different mode as I checked, it may be higher than the typical specification a little as specified in the datasheet but it should definitely be within the min/max range.

BR,

Dale

Dear Dale,

Thank for checking with the evaluation board: offset errors seem very good and according to specifications indeed.

In our solution, the 'External short NOT to AGND' shows an average voltage of 16.8 μV (code of 117.4, LSB 0.143 μV). So much different to the values you showed with the evaluation board.

Analog and digital ground are only connected to each other under the ADS131B04-Q1 and channel 1 inputs are connected across a 22 μOhm shunt resistor in our design. (one side of the shunt is at the analog and digital ground potential) A filter circuit quite similar to the datasheet is present between the shunt and channel 1 input pins.

In the offset error tests, differential filter capacitor C563 was shorted, so quite close to the channel 1 input pins.

Note, adding common mode filter capacitors C562 and C566 (both 10 nF) worsen the offset error to about double the value (28 μV) while the differential mode filter capacitor C563 is still shorted. So there may be something here but I fail to see the root cause.

EDIT 2025-04-24:

NOTE: The above values are internal on the ADC input, thus after programmable gain amplifier (PGA) and not on the ADS131B04 input pins. To get the 'input referred' value, the above values should be divided by 32. The mentioned 28 μV divided by 32 is about 0.88 μV on the input. So within offset error specifications but strange so see such an effect on adding common mode filter capacitors.

Hi Dries,

What's the value of C563 differential capacitor? When you shorted C563, did you try to short them to the AGND according to my suggestion?

BR,

Dale

The value of the differential capacitor C563 is 100 nF. We are measuring DC.

Shorting C563 (shorting both channel 1 inputs) and shorting this to AGND too results in a measured offset error of 27 μV (code of 188.7, LSB 0.143 μV): quite similar to when C562 and C566 (both 10 nF) were placed and quite different to setting the MUX1[1:0] register to 0x01.

It looks like any external short of the inputs to AGND or any common mode capacitance (22 pF, 1 nF or 10 nF) to AGND increases the measured offset error.

Hi Dries,

Is 188.7 the mean code? how many data did you collected from the ADC?

External common capacitors should not increase the offset error, the EVM board has differential and common mode capacitors and I used them to collect the data as shown in the table above.

I'm not sure what caused the difference, are you using a LDO to provide the AVDD power supply for the ADC? Is your board a 2-layer circuit board?

BR,

Dale

Dear Dale,

The PCB is four layer. All lines to the ADC are routed on the top layer and one layer below is a continuous ground. There are no other switching lines under the ADC or under the input lines on other layers. 188.7 is indeed the mean code. This is the mean of 500 samples. In the past we've collected much more samples but the mean and standard deviation did not change significantly above 500 samples. A new single data point for the mean is collected every 500 ms. Total data collection time thus spanning just in excess of 4 minutes with 500 unrelated samples collected to determine the mean and standard deviation (noise).

We do not use a LDO but a buck converter to supply the ADC. There is a low pass filter on the Avcc input. I've already disabled the boost converter on the PCB, cut the power supply to the ADC and supplied the 3.3 V with benchtop laboratory power supply instead but results were the same.

Strange thing is that also with MUX1[1:0] register set to 0x01 gives an offset error measurement of around 4 μV in our case while I would expect it to be like the values you showed with the evaluation board.

I tried to switch the inputs too: both channel 1 inputs have a 2 k input resistance (tried 1 k and 200 Ohm too with no effect) and a 100 nF differential capacitor close to the pins. The positive input would be on about the AGND side of the shunt like in the typical circuit in the datasheet. Switching the resistor connections to the PCB on one side, thus switching the inputs (negative input on AGND side of the shunt) showed a lot of effect in offset error while measuring. Though still not close to the typical expected values:

Switching the inputs would have no effect when the inputs are shorted externally or internally. I mention this as an additional observation hoping that it may give a clue in the cause of the offset error differences that we are observing.

Kind Regards,

Dries

Hi Dries,

LDO is always recommended for ADC, switching power supply will definitely introduce additional offset error, however the layout or other design probably caused this error in your test because you could see a small error when using internal short.

I do not think adding or changing series resistor value will help to reduce the error because our EVM also uses 1kohm series resistors and 1kohm value is not too high to introduce significant noise or have an impact on the offset error measurement.

I'm not sure if you tried a test before, remove the series resistors on both AINP and AINN pins and disconnect the input from the shunt, just short both pins together as close as to the input (probably on the position of 100nF differential capacitor) and tie them to analog ground.

BR,

Dale

Hi Dale,

Thank you for thinking with us. It took me some days to get parts arranged and find some time to test.

ADS131B04 AVCC original supply.
MUX1[1:0] set to 0x00.
2 kOhm input resistors removed.
Channel 1 input pins shorted to AGND
Measured offset error -26.9 µV (Code -188.3)
Very close/comparable to earlier measurements with input resistors in place.

ADS131B04 AVCC supplied through LDO.
MUX1[1:0] set to 0x00.
2 kOhm input resistors removed.
Channel 1 input pins shorted to AGND
Measured offset error -26.3 µV (Code -184.1)
Very close/comparable to earlier measurements without LDO supply

ADS131B04 AVCC supplied through LDO.
MUX1[1:0] set to 0x01: Thus internal short to AGND.
2 kOhm input resistors removed.
Channel 1 input pins shorted to AGND
Measured offset error 3.4 µV (Code 23.7)
Very close/comparable to earlier measurements without LDO supply and not near the expected typical offset of 0.4 µV.

I'm out of options.

Tested lowering the drive strength of all SPI lines too in the mean time without noticeable effect.

Tested providing an external 8 MHz clock instead of the internal 8 MHz oscillator in the mean time without noticeable effect.

Tested adding additional ground plane connections in the mean time without noticeable effect.

I think I'll solder a ADS131M04 in place next week as I do not recall seeing this kind of offset errors when using this chip in the past.

Kind Regards,

Dries

EDIT 2025-04-24:

NOTE: The above values are internal on the ADC input, thus after programmable gain amplifier (PGA) and not on the ADS131B04 input pins. To get the 'input referred' value, the above values should be divided by 32. So within offset error specifications but strange so see such differences between external short and internal short.

Hi Dries,

Did all channels show a similar result? Have you tried another unit? If so, it could be caused by the pcb layout.

BR,

Dale

Hi Dale,

We have four other PCBA with different ADS131B04 showing a very similar offset error of about 17 μV on the ADC input (0.525 μV input referred with a gain of 32).

I may not have been clear by using the ADC input voltages (after PGA). The issue is not that the measured offset error is not within specifications. But that it differs much between power modes (High resolution, Low power) and between external short and internal short (by MUX setting). We cannot calibrate it for one power mode or with the internal short and use the calibrated value for correction in another power mode.

Kind regards

Hi Dries,

Thanks for your clarification. There were some confusions. I thought the values your showed were already divided by the gain.

When you switched between the power modes, did you change the main clock frequency?

Based on your latest information, the offset error in your internal short and external test are within the offset error specification, the difference between them (0.1uV internal vs. 0.82uV external) is definitely caused by the PCB layout.

BR,

Dale

Dear Dale,

Sorry for the confusion, I could have stated input referred values better in the first post.

Switching between power modes is done by setting the PWR[1:0] bits from 10b 'high resolution' (8.192 MHz)

to 01b for the 'low power mode' (4.096 MHz) and to 00b for the 'very low power' (2.048 MHz) mode.

Nothing is done with the main clock frequency as the internal oscillator is used.

I tested using an external clock too, 6 MHz, and values were in between the High resolution mode and low power mode.

Normally I would expect input bias current, or a higher load current when sampling at a higher rate. But there is no voltage on the inputs and they are effectively shorted by the 22 µΩ shunt through which there is no current flowing:

Hi Dries Kooistra,

Dale is out of the office today, he will get respond to your last post early next week

-Bryan

Hi Dries,

Thanks for your clarification on the clock. I previously showed my test result on the EVM in high-resolution mode. I just did one more test in the different mode on the EVM, please see the result below. There is a slight variation with external short in different modes, but all of these results meet the specification of offset error (+/-4uV max/min when the GC is enabled) as shown in the B04 datasheet.

From your latest test result that is shown in the image you shared, most of your test results in HR/LP/VLP mode are within -1.5uV ~1.5uV, all of them are within -2.2uV to +1.5uV, your test results meet the specification too. Your test data in HR mode with MUX=00 are a little bit smaller than other conditions, but this matches my test result on the EVM. I did not see any problem as long as they meet the specification of the offset error.

Let me know if you have any other question.

BR,

Dale