ADS127L18EVM-PDK: TDM mode configuration

Markku Vimpari

Part Number: ADS127L18EVM-PDK
Other Parts Discussed in Thread: ADS127L18

Tool/software:

Single channel works nicely with all tested sample rates 32Ksps - 512Ksps, but we have not been able to find a way to configure ADS127L18 to use two channels in time multiplexed mode with 64Ksps i.e. using only D0 data lane.

Expectation was to get samples from channel 0 and 1so that when there is no signal in channel 0, every second sample value is near zero and status byte carrying channel numbers 0,1,0,1...

Configuration below, can you find an error in it?

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retVal |= ratSpiWriteAds127Reg(GEN_CFG1, 0); // default

retVal |= ratSpiWriteAds127Reg(GEN_CFG2, 0b00000110); // fclk 32.768Hz instead of internal 25.6MHz

retVal |= ratSpiWriteAds127Reg(GEN_CFG3, 0b10000000); // full output slew rate in SAI, comment out for default slower one

// DP_CFG1 Texas suggested 0b01110000, difference in bits 5-4, which would mean 8 data lanes

retVal |= ratSpiWriteAds127Reg(DP_CFG1, 0b01000000); // data port status byte enabled, one data lane

// DP_CFG2 is mode depending

// CLK_CFG is mode depending

// GPIO registers are at default values (low disabled outputs)

// CHn_CFG1 default values (normal polarity, normal range, buffers disabled)

// CH0_CFG2 and CHN1_CFG2 is mode depending

retVal |= ratSpiWriteAds127Reg(CH2_CFG2, 0b00100000); // power down

retVal |= ratSpiWriteAds127Reg(CH3_CFG2, 0b00100000); // power down

retVal |= ratSpiWriteAds127Reg(CH4_CFG2, 0b00100000); // power down

retVal |= ratSpiWriteAds127Reg(CH5_CFG2, 0b00100000); // power down

retVal |= ratSpiWriteAds127Reg(CH6_CFG2, 0b00100000); // power down

retVal |= ratSpiWriteAds127Reg(CH7_CFG2, 0b00100000); // power down

// CHn offsets and gains at default values 0 offset 1.0 gain

switch(sampleRate) {

case 512: // 512Ksps, one channel

retVal |= ratSpiWriteAds127Reg(DP_CFG2, 0b00000000); // DCLK is 32.768

retVal |= ratSpiWriteAds127Reg(CLK_CFG, 0b00001000); // ext clock, div by 1

retVal |= ratSpiWriteAds127Reg(CH0_CFG2, 0b00000000); // OSR32

retVal |= ratSpiWriteAds127Reg(CH1_CFG2, 0b00100000); // power down, using only CHN0

break;

case 64:// 64Kbps, two channels

retVal |= ratSpiWriteAds127Reg(DP_CFG2, 0b00000000); // DCLK is 32.768

retVal |= ratSpiWriteAds127Reg(CLK_CFG, 0b00001011); // ext clock, div by 4

retVal |= ratSpiWriteAds127Reg(CH0_CFG2, 0b00000001); // OSR64

retVal |= ratSpiWriteAds127Reg(CH1_CFG2, 0b00000001); // OSR64

break;

8 months ago

0 Keith Nicholas 8 months ago

TI__Mastermind 48310 points

Hi Markku,

Your configuration looks correct. If you can get a logic or scope capture of FSYNC, DCLK, and DOUT0, that would be helpful to debug the data.

In your configuration, for each FSYNC rising edge, you should get CH0 data immediately followed by CH1 data. In other words, the first 4 bytes will be CH0 and the next 4 bytes will be CH1. You are also getting CH2 through CH7, but since these channels are powered down, you will just get 0x00000000h for each channel.

Each of the channels will look like the below data packet frame, which includes the STATUS byte (no CRC), for a total of 32b.

Regards,
Keith Nicholas
Precision ADC Applications

0 Markku Vimpari 8 months ago in reply to Keith Nicholas

Prodigy 30 points

You are right data words also for the other channels are seen with oscilloscope. The issue has to be in the receiver side in spite of the fact that the number of bits to be received has been set to 64.

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ADS127L18EVM-PDK: TDM mode configuration