• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 193 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1261: System cycle time calculation at 40k ODR

zhaojia
Prodigy 10 points
Part Number: ADS1261

Tool/software:

Hi, 

I am using an ADS1261 designing a force plate with four loadcells, my object is sampling the sensor at 1000hz, according to ads1261's datasheet tab8 and sbaa535a, when I use below parameters, 

filter type: SINC5, datarate:40000, chopping: disabled, # of channels :4, the calculated system cycle time is: (0.179+2*(1/40)) *4 = 0.916ms.

I want to confirm the result, or if there is some wrong calculation, the 1000hz is easy to process for the data analysis.

Thanks very much

  • 0
    TI__Guru 52576 points

    Hi zhaojia,

    I am not sure where the factor of 2 comes into the equation, unless you are planning on taking 3x measurements per load cell: the first measurement completes in 179us, while the other two measurements complete in 1/40000 = 25us. So that means each load cell is measured in 179 + 25 + 25 = 229us, and then all 4x load cells are measured in 916us, which is what you calculated

    If these assumptions are correct, then I agree with your calculations

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 10 points

    Hi Bryan,

    The factor of 2 is using  as the example 7 from Page36 of sbaa535a, I don't understand how to control the Data numbers after the first conversion latency, is determined by our programming or it's a fixed configuration?

    I tried the measurement to an alternative 4xADS1220 solution, but still want to figure out the right information.

  • 0 in reply to zhaojia
    TI__Guru 52576 points

    Hi zhaojia,

    As I mentioned, that factor of 2 in the example in SBAA535A is because there are 3x conversions in that example. Are you taking 3x conversions per input channel? Or just 1? If you are taking 3x conversions, then the "factor of 2" is applicable. If you are only taking 1x conversion per channel, then there is no factor of 2.

    The conversion latency is determined by the ADC based on the ADC settings you choose. For example, if you select a faster data rate, the conversion latency will be reduced

    -Bryan