AMC3336: SINC3 digital filter FPGA implementation

John11513

Part Number: AMC3336
Other Parts Discussed in Thread: ADS1202

Tool/software:

Hi Team,

My customer is designing with AMC3306/AMC3336 for current/voltage sampling. They are considering to implement SINC3 filter in FPGA.

There is an app note for this FPGA implementation: SBAA094. In which 25bits of data bus width is required. However the ideal resolution is 24bit, how should the 25bit filter out be mapped to 24bit conversion result? If you map the 24bit MSB to out, the actual resolution is 23bit. If you map the 24bit LSB to out, the FSR output will be 0.

I noted there is an sample FPGA VHDL code "ADS1202 Reference Design VHDL Software (SLAC055)". In which 24bit of data bus is actually used. There is a bug with this kind of design I think: the output will be 0 once the analog input exceeding positive or negative FSR. Is my understanding correct?

Thank you!

John

7 months ago

0 Eva Mason 7 months ago

TI__Expert 8455 points

Hi John,

Who is the customer and what is their application?

What part of the first app note are you reading this from? Combining ADS1202 with FPGA Digital Filter for Current Msrmnt in Motor Cntrl App.

John11513 said:
If you map the 24bit LSB to out, the FSR output will be 0.

Where do you get this conclusion from? Please let me know so I can better help.

Could you link to the second app note you are referencing as well?

Best regards,

Eva

0 Eva Mason 7 months ago in reply to Eva Mason

TI__Expert 8455 points

Additionally, these FAQs may be good resources for your customer's project:

0 John11513 7 months ago in reply to Eva Mason

TI__Expert 5720 points

Hi Eva,

Thank you for reply.

The customer is CRSC (China Railway). The application is train control system.

You can easily find it through Appendix B and C.

Based on equation (19), page 12, the necessary bus width is 1+K*log2(M). Such for K=3, M=4, the bus width=7. And from Appendix B you can find the filter output code range is 0 to 64. Similarly, for K=3, M=256, the bus width will be 25bits, and the code range will be 0 to 2^24. You will get 0 output if you discard the bit 24 and only output bit 0:23.

The second is not an app, but a VHDL example code. You can find it through link: https://www.ti.com/product/ADS1202?keyMatch=ADS1202&tisearch=universal_search&usecase=GPN-ALT#software-development

Regards,

John

0 John11513 7 months ago in reply to John11513

TI__Expert 5720 points

Hi Team,

Any idea about this question?

Thank you!

John

0 Eva Mason 6 months ago in reply to John11513

TI__Expert 8455 points

Hi John,

Thank you for clarifying your question. To map 25 bits to 24 bits of resolution you can map just the 24 most significant bits. This should be okay since the least significant bit will only be noise and should be only a small variation in value. Hope this helps.

Best regards,

Eva

0 John11513 6 months ago in reply to Eva Mason

TI__Expert 5720 points

Hi Eva,

Thank you for reply.

My question is you can only get 23bits of resolution though theoretically it should be 24bits If mapping 24MSB of the result. Based on the filter logic, the code range will be 0 to 8388608 or 2^23.

Yes, mapping 24MSB will keep most of information. I just want to clarify what is the correct method.

Regards,

John

+1 Eva Mason 6 months ago in reply to John11513

TI__Expert 8455 points

Hi John,

The following excerpt from the AMC1210 digital filter datasheet may help about proper data shifting:

Shifting the data and keeping the 24MSB should work well even if the actual resolution is only 23 bits due to the sign bit. The sign bit should not be affected by a data shift. The last few bits of data are largely noise, and this is the outlined method of data mapping. Please let me know if there are further questions.

Best regards,

Eva

0 John11513 6 months ago in reply to Eva Mason

TI__Expert 5720 points

Hi Eva,

Ok, thank you.

John

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AMC3336: SINC3 digital filter FPGA implementation