Tool/software:
I'm looking for clarification on the expected clock stretching time when averaging is enabled.
My current device configuration is:
OSR = 4 (16 samples averaged, See Table 13, Page 25)
OSCL_SEL = 0 (High Speed oscillator, See Table 4, Page 16)
CLK_DIV = 6 (125 kSps, 8 us cycle time, See Table 4, Page 16)
Figure 24 suggests that the clock stretch time is tconv * OSR_CFG[2:0]. There are a few things wrong with this, 1) how does this take into account the cycle time, 2) the value stored in OSR_CFG[2:0] isn't actually the number of samples averaged.
I'm wondering if the clock stretch time should actually be tcycle * 2^OSR_CFG[2:0]
For my configuration this would give 8 us * 2^4 = 128 us. Here is a capture of SDA and SCL confirming this time.
As others have identified, the TLA2528 datasheet contains errors. Is this another one? When can we expect a corrected datasheet?