Tool/software:
Hi,
I have a set-up consisting of:
- Data generated in FPGA are sent to a DAC using TI-JESD204-IP
- Output of DAC is looped back to an ADC (analog loop)
- Data captured in ADC is received at FPGA using TI-JESD204-IP
After power-up, everything works fine. But, if I reset and reconfigure the DAC, ADC and TI-JESD204-IP, I have a different behaviour: the data received at fpga are coming with a much higher delay than after power-up.
If I keep master_reset_n to '1' during this second reset and reconfiguration, the delay is ok.
Why could this be happening?
I have seen in that the IP is using 4 BRAM per Tx lane, so I guess the delay comes from these BRAMs.
Thanks in advance
Miguel
