ADS8684: SCLK rising edge to SDO valid

Thank you for your answer.

From the timing diagram you drew, is my understanding correct : Even if the frequency of SCLK is reduced, the valid SDO width in the worst case is still 35ns?

As shown in the figure, when the SCLK frequency is reduced to 12.5MHz, the valid SDO width in the worst case is 35ns.

Or, to be more extreme, when the SCLK frequency is reduced to 1MHz, the valid SDO width in the worst case is 35ns.

In other words, the valid SDO width is independent of the SCLK frequency.

The SDO is intended to be read by the processor on the falling SCLK edge.  A slower SCLK will give more setup time (longer valid time) but it won't increase the hold time. 

Could you please provide the specific quantitative relationship between reducing the frequency of CLK and increasing the setup time of SDO？

In this application:

The digital isolator will cause a delay in the signal from input to output, with a maximum delay of 18ns and a minimum delay of 0ns.

CLK period is set to 60ns (50% duty cycle).

The waveform in the worst case is:

The waveform in the best case is:

The best-case and worst-case waveforms put together are:

The time interval (b->c) in the figure is 41-5=36ns > 35ns.

There is no overlap between the valid SDO of the best case and the worst case, and it brings risks regardless of when sampling is chosen.

If I set the CLK cycle to 80ns, can the setup time be increased by 10ns ?
In this case, the time interval (b->c) is 41-5=36ns < 45ns, and the processor can have 9ns for sampling.

If I set the CLK cycle to 100ns, can the setup time be increased by 20ns ?
In this case, the time interval (b->c) is 41-5=36ns < 55ns, and the processor can have 19ns for sampling.

Hi Zhaoyu,

If you slow down the clock, yes, your setup time technically will increase.  You need to consider the max delay through the isolator on the way in for your SCLK and for SDO on the return trip.

Hi Tom

"A slower SCLK will give more setup time (longer valid time)"

Does this mean that if the SCLK period is longer as shown in the figure below, the valid time will be longer by the same amount as the longer period (58.824ns in the figure below)?

Yes, that is correct.