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DAC81404: SPI_interface, voltage_reference, power_requirements, operation_mode

Sam_
Prodigy 30 points
Part Number: DAC81404


Tool/software:

Dear TI Support Team,

We are evaluating the DAC81404 for use in a precision analog output module and would appreciate your confirmation on the following technical points based on the datasheet (SLASEH2A – NOVEMBER 2020 – REVISED MAY 2021):

Question 1: Is 3.3 V acceptable for DVDD?

In section 7.3 Recommended Operating Conditions, the DVDD (digital supply voltage) is specified as:

4.5 V to 5.5 V

We initially assumed that 3.3 V might be acceptable, but based on this range, it appears unsupported.
Can you confirm:

  • That 3.3 V is not valid for DVDD, and

  • Whether using 3.3 V might lead to undefined behavior or logic level incompatibility?

Question 2: Can the SYNC pin be used as SPI chip select (CS)?

Our SPI master interface expects to use a conventional chip select (CS) signal. In section 8.5.1 Stand-Alone Operation, the datasheet mentions:

“The SPI protocol used is a standard 4-wire interface with a chip select (SYNC), serial clock (SCLK), serial data input (SDI), and serial data output (SDO).”

This suggests that SYNC serves as CS in a standard SPI configuration.
Can you confirm that SYNC is functionally equivalent to a chip select (active low) signal?

Question 3: How is Stand-Alone Mode selected or configured?

Section 8.5.1 describes the stand-alone SPI operation mode, but it is not entirely clear whether any specific pin strapping, register setting, or boot-time condition determines this mode.

Could you clarify:

  • How the stand-alone mode is selected?

  • Whether the device automatically defaults to this mode at power-up?

Question 4: Performance expectations when using an external reference like ADR411

The DAC81404 includes an internal 2.5 V reference with:

  • ±5 ppm/°C typical temperature drift

  • 5 ppm typical initial accuracy (section 6.6)

We are considering using an external reference such as ADR411 (±3 ppm/°C drift, 0.04% initial accuracy).
Would this provide noticeable performance improvement in long-term stability, gain accuracy, or output noise?

Thanks and regards

Ismail 

  • 0
    TI__Mastermind 42273 points

    Hi Ismail, 

    IOVDD is the logic level and can support 3.3V logic with a 3.3V supply. DVDD and AVDD supply internal digital and analog blocks in the device and won't work at 3.3V. 

    Yes, SYNC and CS are equivalent in this context and is active low. 

    Stand alone is the default and just refers to one SPI CS used to control one DAC. The alternative is daisy chain where one CS is used to control multiple DACs. The SDO pin needs to be enabled to use daisy chain mode. SDO can also be used in stand alone mode to read back from the device, just note that first 24-bits of the SPI frame are used when SDO is disabled, and the last 24-bits of the SPI frame are used when SDO is enabled. 

    I assume you mean ADR441. It looks like the ADR441 is better performance than the DAC internal reference for the specs you pointed out. We share all of those specs in the datasheet:

    I can't answer whether this will be a meaningful/noticeable difference to you. That depends on your application accuracy requirements. The reference error could be considered the initial accuracy of the DAC, and our DAC error is pretty small compared to either reference error. You will see the difference in reference error if that is generally what you're asking. 

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    Prodigy 30 points

    Dear Katlynne Jones,

    Thanks for the clarification. I would like to confirm the appropriate supply configuration for generating 0 to 10 V analog output signals.

    If I provide the following supplies:

    • VDIO = 3.3 V (for compatibility with a 3.3 V MCU),

    • DVDD = 5 V,

    • AVDD = 12 V,

    • AVSS = –12 V,

    Would this configuration allow the DAC81404 to generate a full-scale unipolar 0 to 10 V output on its analog channels?

    I understand that the output voltage range is determined in part by AVDD/AVSS and the internal reference settings or external reference. Could you confirm whether the above supply configuration is valid and sufficient for 0–10 V output, and whether there are any special configuration registers or constraints I should be aware of?

    Thank you for your support.

    Ismail

  • 0 in reply to Sam_
    TI__Mastermind 42273 points

    Hi Ismail, 

    Yes, these supplies are fine. The DAC requires 1.25V of headroom from AVDD and 1.5V of footroom from AVSS when sourcing/sinking 10mA. So +/- 12V supplies will be fine for 0-10V. You could tie AVSS to ground since you only need a positive unipolar output, but you will see slightly reduced performance when trying to drive a load at 0V. 

    You set the output range in the DACRANGE register. There is a setting for each channel. The internal reference is powered down by default, so you need to power it on in the GENCONFIG register. The DAC outputs are powered down by default, so you need to power them on in the SPICONFIG

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    Prodigy 30 points

    Hi Katlynne,

    Thank you very much for the clarification. This is exactly the information I needed.

    Much appreciated!

    Best regards,
    İsmail