We are using ADC ADS8330 in our project for data acquisition for sampling data at rate of 1Mhz.
We are facing a problem wherein sometimes the EOC signal always remains high and sometimes it does not stay low for required duration i.e. 18CCLK's
The procedure for generating the control signals is explained below.
The conversion clock for ADC is the Internal Osc clock of 21Mhz.
Points considered for generating the control signals inside FPGA:
1. The minimum time between two consecutive CONVST signals is 21 CCLKs (conversion clocks)i.e. > 900 ns FPGA is generating convert start every 1usec
2. A low CONVST pulse of 100ns.
3. assert the chip select line ( active low)
4. 40ns delay between falling edge of CONVST and rising edge of SCLK
5. SCLK frequency is 25Mhz. sampling the data on the falling edge of the SPI clock
Note: we are not checking the EOC since we have already maintained the timing between issuing two consecutive convert start as > than 21 CCLK.
EOC should be generated from ADC after a convert start is issued
Can you please provide some solution or inputs for solving this.
Regards,
Priya.
