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TSW12QJ1600EVM: FPGA Reference Clock

Hiroshi Oinuma
Prodigy 10 points
Part Number: TSW12QJ1600EVM
Other Parts Discussed in Thread: ADC12QJ1600EVM, LMK04828, ADC12QJ1600

Tool/software:

I have a question regarding the TSW12QJ1600EVM GUI.
When I set the following configuration, the FPGA Reference Clock is displayed as 167.578125 MHz.
#1. Clock Source: OnBoard 50M Ref to ADC PLL
#2. On-board Fs Selection: Fs = 1300 Msps
#3. Sampling and Calibration Mode: JMODE6

However, when I set the same configuration in the ADC12QJ1600EVM GUI, the FPGA Reference Clock is displayed as 162.5 MHz. What could be causing this difference?

  • 0
    TI__Expert 6150 points

    Hello,

    In the TSW12QJ1600 EVM GUI the reference clock to the FPGA is supplied by the ADC itself, where it take a divided down version of the serdes rate. Whereas for the ADC12QJ1600 EVM GUI the reference clock to the FPGA is supplied by an external LMK04828 device where the ref clock is a different divided down version of the serdes rate.

    For the mode you have selected and the sampling rate the serdes rate will be 1.3GHz*8.25 = 10.725 Gbps = 10725 Mbps.

    For the ADC12QJ1600 EVM the reference clock is divided down by 66 to get a frequency = 162.5 MHz. 

    For the TSW12QJ1600 EVM where the reference clock is supplied by the ADC itself, the available dividers are /16, /32, /64. In this case the /64 option is chosen which gives us a final reference clock rate of 10725/64 = 167.578125 MHz.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 10 points

    Thank you for your response.

    Is it correct to understand that the FPGA Reference clock displayed in the GUI is the GBT clock?
    In the ADC12QJ1600EVM, when “OnBoard 50M Ref to ADC PLL” is selected,
    I think that the LMK04828 is not used as the clock source.
    Therefore, if the /64 option is selected, I think 167.578125 MHz should be displayed. Is this correct?

  • +1 in reply to Hiroshi Oinuma
    TI__Expert 6150 points

    Hello,

    In the ADC12QJ1600EVM the FPGA reference clock displayed is the GBT clock as well as the application layer clock. In the Onboard 50MHz mode it is not accurate as the ADCs trigout clock is used as the GBT clock and the PLLREFO is used as the application layer clock, this is not displayed in the ADC12QJ1600 gui.

    Thanks,

    Eric