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Original question:

TSW3085EVM: TSW3085EVM QMC SETTINGS

TSW3085EVM: Digital mixer and SFDR problems

Yigit SARI
Prodigy 40 points
Part Number: TSW3085EVM

Tool/software:

My system is working with 1250MHz Fdac, 312.5MHz Ffpga. I am generating 312.5 MSPS 20MHz sine signal from FPGA. LO frequency is 1GHz. I am in single sync source mode and NCO is off. I am using ZCU102 as FPGA.

I have a question about digital mixer. I set the interpolation value to 4x to keep the sample size the same. I keep Digital Mixer in Bypass mode in Enable.

 

The spectrum view of these settings is as follows.

When I disable the Mixer from the GUI, I can receive my signal properly.

What is the reason for this and how can I fix it?

Also, another question I want to ask is that when the settings are “fDAC = 1.25GSPS, fOUT = 20MHz” I see 70dBc instead of 82dBc as SFDR value as mentioned at Datasheet. What could be the reason for this?

  • 0
    TI__Guru* 78744 points

    Hello,

    When you enable digital mixer, you need to enable digital NCOs or set the mixer to be multiples of fs/8. Otherwise, if you do not plan to use the digital mixer, then please disable the part. Please refer to following app note for detail:

    https://www.ti.com/lit/an/slaa584/slaa584.pdf

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 40 points

    Hi Kang,

    I did what you said. In my draft project, I want to run the digital mixer only at multiples of fs/8. I'm working with the following settings in the GUI.

     

       

    Eval board settings are: VCO 2400MHz, DACCLK 800 MHz, FPGA CLK 120MHZ, DAC internal pll 960MHZ, 10MHz sine tone, TRF LO 1445MHz.

    The image below on the left is fs/8, and on the right is the signal mixed at fs/4. I can only see a proper spectrum at fs/8. Other digital mixer settings also produce a distorted spectrum, like fs/4. 

                                              

    What might be the cause of this? Thank you.

    -Yigit

  • 0 in reply to Yigit SARI
    TI__Guru* 78744 points

    Hello Yigit,

    Could you please disable clock divider sync once the TSW3085 is configured? 

    When clock divider sync is always enabled, the FRAME signal will constantly synchronize the clock divider, and will reset the internal digital logics. 

    Please see below app note for detail:

    https://www.ti.com/lit/an/slaa584/slaa584.pdf page 26

  • 0 in reply to Kang Hsia
    Prodigy 40 points

    Hello,

    I adjust settings based on your feedback, but there is no change in the output spectrum.