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ADC12J4000: DEVCLK amplitude vs jitter

Geir
Intellectual 335 points
Part Number: ADC12J4000
Other Parts Discussed in Thread: ADC12J1600, , ADC32RF45, LMX2820

Tool/software:

Hi,

we upgraded a design from ADC12J1600 to ADC12J4000 but are struggling with performance issues.Among the things changed was the clock tree.

Reviewing the datasheet for ADC32Rf45 we noticed that there is a clear relationship between the DEVCLK amplitude and jitter, which again goes against SNR.

Does this relationship exist for the ADC12J4000 too? Fs is 4GHz.

We are using the LMX2820 as final synth which provides 6dBm into 50 ohms. But the bandpass filter drops 2 dB, so it's marginal. 

  • 0
    TI__Mastermind 37660 points

    Hi Geir,

    I am seeing if we have any data that reflects SNR vs. Clock amplitude. This seems to be what you really need.

    in general you want to make sure the amplitude and slew of the clock edge is at its maximum when the clock signal arrives at the pins of the ADC.

    This yields the best performance. Adding filters in line with the clock is a good ideas when it comes to removing clock spurs and other noise, but it also decreases the slew edge.

    Typically what customers do is provide an LNA, then filter. The just back off the LNA gain as appropriate to ensure they are within the abs max of the clock pins.

    Another question I have, when using the J1600 and now the J4000. Are you using a higher band of frequencies? Or the same band of interest? If a higher band of frequencies, then this will also lead to further degradation, as your current clock signal chain is becoming jitter limited.

    Regards,

    Rob