Other Parts Discussed in Thread: CDCE62005,
Tool/software:
Hello,
I am experiencing some difficulties in the usage of the DAC3484 on my PCB. the system that I am using is a FPGA card cunnected to a PCB with two DAC3484 and a CDCE62005 that supplies them with clocks.
Currently I would like to address a specific problem- The PLL isn't locking. I tried various combinations of N, M, P and VCO_tuning_bits. Example shown in attached image:
I communicate with the modules through the FPGA card, and I am familiar with the fact that N should be written as N-1 to the DAC (when I wanted to insert 8, I sent 7 to the pll_n register in config25).
The when I check reg5 I get 0x0060/0x0020, which means the alarm_from_pll is the only alarm bit on, and the ATEST through TXENABLE went good. I got the recommended external loop filter connected through the A1 pin of the DAC.
My DAC is of version 100b so I check the pll_lfvolt to see if I'm locked, but it gets 111b regardless to the PLL values I give it.
If anyone encountered some sort of similar problem, please share your knowledge about the solution of this problem.
Tom
