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ADC12DL1500: Sweeping input clock

Part Number: ADC12DL1500

Tool/software:

Dear TI support,

I'm reaching out to you with a special requirement in our application that I would like to clarify with you:

Is the proposed ADC capable of receiving input clock that sweeps/steps from 500MHz to 1.1GHz in several smaller steps and then back to 500MHz. After each step the sampling clock would stay constant for a certain time. Is this OK, or would this confuse the ADC?
What would be the impact on the outputted data-clock?
Would using Sysref clock make any sense in such an application?
Thank you,
Simon
  • Hi Simon,

    Yes, it is possible to do this, but there are some things to think about.

    First, if there is any calibration done, then you need to factor in time for a re-calibration and for the sampling clock to settle.

    Then you need to wait a number of samples in order for the converter pipeline delay or latency to clear before you have another valid sample.

    Regards,

    Rob

  • Dear Rob,

    Thanks for taking the time.

    Interesting! Is calibration dependent on the actual sampling clock? Is there a diagram of inaccuracy vs clock uncalibrated?

    How many samples would we loose if we sweep 1% step in frequency. For example from 1GHz to 1.01GHz.

    Would the ADC data clock reflect this change in sampling clock immediately or at least deterministically? I ask because if I need to "skip" samples, I need to know skipping happens. This is not planned as of now. Can I read it from the data clock?

    Would you be open for a review of schematics and further discussion?

    That would be highly appreciated!

    Kind regards,

    Simon

  • Hi Simon,

    We just don't have that type of data, as this is a non-standard use case. It might be best to measure this on your own using an EVM.

    Yes, we can review schematics, etc when you have that ready. Please open a new post.

    Regards,

    Rob