• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 46 subscribers
  • Views 270 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS825E ramp up problem

Lingli Liu
Prodigy 210 points
Other Parts Discussed in Thread: ADS900

Hi,

We connected an ADS825E  according to the recommendations in Figure 2 from the data sheet, and connected IN port to the Vcm biased by two 1.62K resistor (the resistors are not very accurate and we saw a non-zero shift of the sampled data).  We expect to see a straight line reflecting the Vm voltage but we observed a ramp up in the sampled data. 

The ADC clock was 40Mhz and we generated about 300 clocks to sample the Vcm into a fifo, then used a computer to read this fifo and drew the plot.  BTW all the bypassing capacitors for power supply and ref-voltage pins were selected according to the SPEC.

Any suggestion about the reason why there is such a ramp-up even we sample a common voltage?

Thanks a lot and happy new year!

Lingli

  • 0
    TI__Mastermind 29220 points

    Hi,

    So if I understand your description of the setup, you expect to see a DC signal at the one input pin that is being used, relative to the VCM voltage at the other input pin, and so you expect to see a flat line.  But the DC voltage at one input pin is derived from your supply while the other voltage is generated internally in the data converter.

    It would be interesting to see a longer capture than the 300 samples, or at least more than what looks to be about 70 samples or so in the plot you included. I would not expect drift due to temperature or voltage over time to have that much slope to it, so I wonder if you are seeing a portion of a periodic wander to the input voltage.  At 40Msps, the portion of the plot you showed would represent about 2 us of time.  If there were a noise component on the supply that were in the KHz range, like around 10KHz, then that could be seen on the input voltage derived from your resistor divider but not on the voltage from the VCM pin and you might be seeing a portion of that periodicity.  That would be my first guess. 

    Regards,

    Richard P.

     

  • 0 in reply to Richard Prentice
    Prodigy 210 points

    Hi, Richard,

    Thanks a lot for your reply!

    Here is more information for you about this issue:

    The board we are using is designed according to previous project in which we were using an ADS900.  The only difference between

    these two boards are the connections of ADS900 & ADS825E, and all other parts including power supply system are the same. In the old board,

    ADS900 works well with 20Mhz sample clock, no voltage slope observed when we put a DC on the input port (please note two boards

    are both single-supplied). In the new board, we have tried to sample with the same 20Mhz clock but voltage ramp is here as well. We also changed

    the DC input from our amplifier to Vcm biased by REFB/REFT to exclude the effect from our power, and the ramp is the same.

    I hope this info can be helpful. 

    Lingli

  • 0 in reply to Lingli Liu
    TI__Mastermind 29220 points

    Hi,

    It still seems to me that a ramp cannot go on forever, so I expect it is not so much a ramp as a portion of a low frequency component getting into the signal.  A longer window of capture either prove or disprove that, and if a long enough capture is observed such that the period of the component can be observed then you would have an idea of what to look for, either a componenet of that frequency riding on the supply or possibly coupling in from somewhere else on the board. 

    Your first posting suggested that the DC input you are creating is from two 1.62Kohm resistors forming a voltage divider.  I understood that to maybe mean that you were using the supply voltage on the board across the voltage divider, but I think now you are saying you are putting that voltage divider across REFT and REFB to create the DC voltage to be near VCM?    That would be a good way to create this voltage and is suugested as such in Figure 7 ot the datasheet.  I would not expect a low frequency noise component to appear given this setup.  What do you see if you hook the internally generated VCM voltage to both the IN+ and IN- pins, essentially shorting the input together to get 0V differential but at the desired common mode level?  Do you have bypassing on the ByT and ByB pins, which are two more pins to have bypass caps on than the ADS900 had?

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 210 points

    Hi, Richard,

    We did 2 further tests on the board,

    1. Shorted IN with ~IN and CM, and got a flat line with very low noise.

    2. Changed the 0.1uf bypass capacitors on CM and ~IN ports to 1uf, then the ramp is also gone no matter what DC we use to connect with IN (from power supply or bias from REFB/T).  Yet the 0.1uf capacitor is recommended in the data sheet.

    By the way, we have 0.1uF capacitors on all the power supplies and ref pins including ByT ByB as recommended from SPEC.

    Does this make sense to you?

    Thanks!

    Lingli

  • 0 in reply to Lingli Liu
    Prodigy 210 points

    Hi, Richard,

    We tested it again and found if we use 1uF bypass capacitors on CM and ~IN,  the ramp is still here but gets much smaller.

    If we removed the bypass capacitor the result will be even better and there is almost no ramp.

    Lingli