ADC12D1620QML-SP: Unexpected Data output when analog data is input

Hi,

Yes, when there is no analog input signal applied to the ADC. The expected output, digitally, should be centered at mid-code of the ADC. Plus and minus a few LSBs.

Q1. According to datasheet, when user set "AC coupled input", it seems that 1.25V is applied as common mode voltage for analog input. RR: yes, correct.
When analog input with 0V common mode voltage is applied to analog input without AC coupling, RR: yes, correct. is phenomenon which we observe middle value(800h) on digital output expected behavior ?RR: yes, correct...as described above.

If you can share some output data that you have collected and your analog input network interface circuit to the ADC. This would be helpful as well.

Regards,

Rob

Hi,

Thank you for your reply.
>Plus and minus a few LSBs.
Do you have any reason about why above condition wiil be obasrved when there is no analog input ?

Best Regards,

Hi,

>Not sure I understand your question. You mean why are there a few LSBs "moving" being seen while capturing with no analog input applied?
Yes, and I understood about this.

I have another question.
In this case (no analog input), how ORI (or ORQ) will behalf ?
According to description of ORI and ORQ, these are asserted when analog input is out of range for FSR setting.
Specifically, when ADC driver amp's common mode voltage is set as 0V (as I described first thread.), ORI or ORQ should be asserted ?

Best Regards, 

Hi Ryuuichi,

The ADC driver common mode voltage should 1.25V if you plan to DC couple to the ADC.

If you push the common mode too low and directly connect to the ADCs analog inputs, then yes, the ORI/Q could be asserted, as this would be out of FSR.

If you send over a schematic on what you are planning to do, I can look it over.

Regards,

Rob

Hi,

Sorry for confusing you.
I will explain background of this question.

As I said on first thread, customer faced following issue.
* customer is now observing approx 800h even though they input analog data (approx 500mVpp)

Here are detail about above.

1. Customer input 500mVpp signal (+/-250mV)
2. Customer set 0V as common mode voltage for ADC driver (they use THS4541 for ADC driver)
3. Customer set "AC coupling" mode to ADC. However, they did not implement AC coupling capacitor.
=> Root cause of this issue was above. After implementing AC coupling capacitor on Vin line, they observed expected result.

However, they observed following condition even though they input CLK(500MHz) to ADC.
* They observed "ORI" was "Low" state.

According to datasheet, "ORI" will be asserted not only greater than FSR but also less than FSR.
In above case, input signal is less than FSR (FSR is 1.25V +/- 315mV). So we thought that "ORI" will show "Hi" state. But result was different.

So, I asked this question.
Can you explain why "ORI" was NOT asserted to "Hi" in above condition ?

Best Regards,

Hi Ryuuichi,

If ORI is still asserted, then the inputs of the ADC are still not within range.

If might be best the customer probes both of those inputs and makes sure they are exactly the same.

If they are not the same, then the ADC fullscale range will be over-ranged. You would also be able to test this by collecting an FFT output spectrum.

Regards,

Rob

Hi,

>If ORI is still asserted, then the inputs of the ADC are still not within range.
You may misunderstand my situation. Let me re-explain about my situation.

>However, they observed following condition even though they input CLK(500MHz) to ADC.
>* They observed "ORI" was "Low" state.
Above condition was occurred under "without AC coupling capacitor even though they set "AC coupling mode"".
When ORI function worked correctly, I believed "ORI" should show "High" for this wrong condition.
However "ORI" showed "Low" in this wrong condition even though input data for ADC was less than FSR.
Therefore, I asked trigger condition about "ORI"(ORQ) function.

Best Regards,