DAC8812: Design Inquiry

Part Number: DAC8812
Other Parts Discussed in Thread: ADS127L18

Tool/software:

Hi Team,

My board clock requirement block diagram is attached below.

The clock from the clock synthesizer need to feed as input clock to all ADC, DAC and FPGA in the board to make a synchronization.

Also from FPGA an input SYNC IN/ LDAC like input signal is fed to all the ADCs and DACs so that FPGA can control and sync activities of all the data converters.

My requirement is 16-bit 33MSPS SPI DACs (single or dual channel). We look upon on SPI DACs because of less pin input for SPI. But I didn't find any SPI data with CLK IN pin .

Then i searched LVDS and CMOS DACs, there i could get CLK IN as per my requirement. But these CMOS input signals for DAC8812 are 16+16, 32pin data inputs along with several control signals. But i required 4-5 DACs in the board, if i use 5 DACs total input pins from the SOM/FPGA must be minimum 32*5 160data input pins. I can't afford that much pins from my FPGA. So can you please suggest a DAC for my requirement that less no of input pins. LVDS DACs is also fine for my requirement, but i must a single P/N input signal for the DAC, but 16P/N inputs signals for a single DAC, i can't give.

Please provide a suggestion for my query.

Regards,

Abhishek

  • Hi Abhishek,

    With the DAC8812, could you use a common SCLK, CS for all 5 devices, 5 dedicated SDI lines, and then a single, shared LDAC for all 5?

    Thanks,

    Paul

  • Hi Paul,

    I can't use SCLK as a common clock, because the same clock from a master clock (like a clock synthesizer) need to be given to ADC, DAC and FPGA.

    I'm using the ADC IC ADS127L18, that IC has a dedicated CLK IN pin so that i can give my clock input to the IC. Same is the requirement for the DAC also. But i can't use LVDS input DACs as i have less input pins available in my FPGA.

    Please suggest a part for my requirement.

    Regards,

    Abhishek

  • Just to be clear: the DAC8812 does not operate on some kind of master clock.  The device has no closed-loop functions or state-machine besides the SPI input register.  The SPI does not require any precise or regular clock.  If you are trying to synchronize the dac updates, it is only critical to synchronize LDAC.