Hello, with an external 16Mhz input on CLKIO, I am trying to just read a status register every 1ms. At 1ms, the SPI interface is being reset every cycle (because the default reset occurs after 4096 fclks, or ~250us). I think the SPI interface reset means all registers are set to default, but I don't see that explicitly stated.
Thanks,
Jim
Hello Jim,
When SCLK is low for more than 4096 fCLK cycles (or 256 fCLK with SPIRST=1), only the SPI interface is reset; similar behavior when setting the /CS pin high in 4-wire SPI mode. The register values are not reset and will remain in their current state.
This feature is useful to recover communications due to a glitch on SCLK when using 3-wire SPI mode with the /CS pin constantly tied LOW.
There is a little more clarification on this behavior in the SPIRST register setting section of the datasheet.
Regards,
Keith Nicholas
Precision ADC Applications
