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AMC131M01: About step response time

Hiromu Susami
Intellectual 1400 points

Part Number: AMC131M01

Hi exparts,

Q1. What kind of setting should I set when I want to achieve a rise time of 100us for step input? The rise time is the time when the digital output of the ADC is 10% => 90%. 

Q2. How much is the accuracy worse for an ADC output rise of 20us?
I/O response tends to deteriorate if the OSR is increased in order to improve accuracy with the ADC, so I would like to confirm the trade-off relationship.

Example waveform: (top row: ADC input, bottom row: ADC output) 

Regards,
Hiromu

  • 0
    TI__Expert 7550 points

    Hi Hiromu,

    Please refer to the below 2 tables to determine the settling times and ENOB based on the OSR setting.

    Thanks.

  • 0 in reply to Saleh Ahmad
    TI__Intellectual 1400 points

    Hi Saleh,

    To achieve 100usec output rise time, can I simply calculate like this?: 

    100usec < t_CLKIN x settling time(total)
    (*T_CLCIN = 1/8.192MHz)
    settling time(total) < 100usec x 8.192M = 819.2 

    To achieve 10usec, settling time(total) must lower than 81.92. How can we achieve this? Use faster clock like f_CLKIN = 40.96MHz?

    Regards,
    Hiromu

  • 0 in reply to Hiromu Susami
    TI__Expert 7550 points

    Hi Hiromu,

    The AMC131M0X device is targeted for low bandwidth, high accuracy measurements and its max data rate is 64ksps, so you wouldn't be able to get data out from the device within 10us. 

    What application are you designing for?  If you need a high bandwidth, you should look at our isolated amplifiers and modulators.  

    The amplifier devices have fixed filter settings and the output should settle within a few us.

    The modulators are more customizable for the bandwidth/resolution tradeoffs since the filtering would be done by the MCU.

    Thanks.

  • 0 in reply to Saleh Ahmad
    TI__Intellectual 1400 points

    Hi Ahmad,

    I'm sorry, 10 usec is not true, 20 usec is the right time. Is it passible to achive 20 usec by 64ksps(15.625us) data rate if we use faster F_CLKIN?

    Application is Protection reray. We require DC test signal function. That's why we are considering this ADC. 

    Regards,
    Hiromu

  • +1 in reply to Hiromu Susami
    TI__Expert 7550 points

    Hi Hiromu,

    For a step input to fully settle it with the max Fmod of 4.096MHz and OSR of 64 it would take 240 clock signals, which would be ~58.6us.  This is because it goes through a 3rd order sinc filter, you need 3 cycles for the step input to fully go through the filter.  

    You would still see the output change in the 1st and 2nd captures, below is how a pulse being measured by the device would look.

    Thanks.