ADS54J60: Missing test setup for ADS54J60. Unable to reproduce ENOB for 2nd Nyquist from datasheet.

Bartosz Szkoda

Part Number: ADS54J60
Other Parts Discussed in Thread: LMH5401

Our design has ADS54J60 with fs=1Gsps. The goal is to capture signals from 1st and 2nd Nyquist. Datasheet specifies that at 720 MHz, we should get ENOB of approximately 10.5 bits (table in section 7.6 AC characteristics).

We generate the signal using 50 Ohm RF signal generator, use a pass-band filter at 770 MHz +-20Mhz (ZX75BP-770-S+) and plug it into our custom board. The signal power corresponds to half of the ADC scale, as recommended in the datasheet for this range of frequencies. We configure the ADC for interleaving correction at 2nd Nyquist. The input structure is as follows (the output of this circuit goes directly to ADC inputs):

The resulting performance is very underwhelming. We cannot get more than 9 bits of ENOB. It's usually something around 8.3-8.6 bits for different hardware configurations.

I suspect that it is due to input impedance of ADC drastically dropping above 300-400 MHz and balun being unable to drive such a low impedance. We had another board with the same ADC but also a driver at the input, the LMH5401. We setup RC elements at the board for AC coupled input and DC coupled output (thus ADC is DC coupled with the driver) with gain of 2 V/V (changed from 4 V/V that is on the figure below using recommended component values from tables in opamp's datasheet). Also, CM port is not grounded, but connected to ADS54J60's Vcm output.

This setup resulted in ENOB of 9.4 or 9.6 bits, depending on Input DC coupling in ADC registers being, respectively, disabled or enabled. We also have a simple 3rd order LC lowpass filter with bandwidth of 1 GHz between a driver and ADC but it should not affect performance at all. So we are still missing almost 1 bit of ENOB.

I suspect that the configuration with opamp driving ADC inputs may yield the ENOB specified in datasheets, but we cannot know for sure as we have no reference test setup in the ADC datasheet. Another limiting factor might be jitter. On the board with OpAmp we use LTC6952 clock generator with CVCO55CC-4000-4000 as VCO. On the board with balun we use HMC7044LP10BE with CVHD-950X-50 as VCO. Clocking analysis tools say that we should get at least 10 bits of ENOB for the balun board according to estimated jitter.

So I request to either review our RF inputs structure or supply us with reference test setup so we can reproduce the ENOB specified in the ADC's datasheet.

5 months ago

0 Rob Reeder 5 months ago

TI__Mastermind 45670 points

Bartosz

Hi Bartosz,

Please send me the details of your test setup. A block diagram would be easier for us to understand.

Most likely you are not using a "clean" enough/low phase noise clock of there is something in the signal chain that is making all the noise fold back inband.

Just to confirm, this a TI EVM or your own customer built board?

Please advise.

Thanks,

Rob

0 Bartosz Szkoda 5 months ago in reply to Rob Reeder

Prodigy 30 points

This should be sufficient, I believe.

Yes, both boards are custom. The board with OpAmp is similiar, but instead of balun you have LMH5401 OpAmp (2 V/V, AC coupled configuration) and for clocking instead of HMC7044 + CVHD-950X-50 combo you have LTC6952 + CVCO55CC-4000-4000.

I would also like to note that previously for the balun board we used CVHD-950X-100, which has at least 0.5 GHz bandwidth of stronger phase noise than the current CVHD-950X-50 and it still did not affect the ENOB. We have tripple checked the clock setup, we based our design on Analog Device's evaluation boards with this clock, we have verified the design with clock simulation tools. This is why we veer towards the issue root being the AFE and/or the ADC, hence this post.

However, I am open for inspection of our clocking solution.

0 Rob Reeder 5 months ago in reply to Bartosz Szkoda

TI__Mastermind 45670 points

Hi Bartosz,

Thank you for the details. this helps.

Please try the following, turn off the analog input sig gen or disconnect it.

Then capture an FFT plot and see if the noise floor goes down. Gets lower than the pervious plot you sent over, above.

This will prove if the clocking signal chain you have is good enough for your application.

If not, and your noise floor is roughly the same, then you may need to speak to someone at ADI on how to properly config the HMC7044 device to achieve better phase noise.

Regards,

Rob

0 Bartosz Szkoda 5 months ago in reply to Rob Reeder

Prodigy 30 points

Here are 3 FFTs: half-scale signal at input, terminated input with 50ohm load, floating input (ignore the filename string in the figure). I see a few dB drop in noise. Help me judge wether this is a significant drop in a noise floor level (please ignore the SINAD, ENOB etc. in terminated and floating input FFT figures) or not and issue may really lay in the clocking.

half-scale signal FFT: