I would like to get your support in an issue we have encountered in our product that relates TI ADS62P29.
Issue description:
You can see in the below block diagram that there is an internal CLK and an external one. The internal CLK will be used as a back up if the external clk from some reason fails.
Both of these clk's are almost the same frequency, different in some Hz, but they are not in phase with each other. They are both TCXO sources which are kept live in the application. If the external CLK fails the CLK switch, switches to the "live" internal clk source, keeping the system running. (similar function to a holdover I guess) this clk is fed to the CDCE62005 which is the source of the FPGA PLL CLK Circuitry and the sampling CLK of the ADC. In order to collect the samples correctly from the ADC. The ADC output CLK (clk out in the block diagram, [the output data clk, not the sample clk]) is an LVDS clk which is fed to the FPGA which collects the data. The main problem as furely described below is that when the clk switch switches from one clk source to the other, the LVDS eye of the clk out of the ADC closes and the levels are small that the FPGA doesnt detect it, leading to a miss in reading the input data and a fault packet, which needs to be re-sent. Here is the description:
At Product level - There is FER during switching the CDCE Reference clock.
- no relation to signal SNR.
A high level block diagram :
The ADC is TI ADS62P29, the FPGA is an Altera Stratix IV, (EP4SE360H29C2N) and the CLK switch is Hexawave, HWS429
The internal and external Clocks frequency is 10MHz, still the frequency is not equal in Hz level, and the clock are not synced in phase.
The ADC is configured to DDR mode.
ADC Sampling clock input pins at ADS62P29: 25,26
ADC clkout pins at ADS62P29: 56,57
The sampling clock is provided by TI CDCE62005, clock type : LVPECL, 200MHz
CDCE Sampling clock output pins : 27,28 (out 0).
Detailed description:
Figure 1 describes The CDCE62005 output clock to ADS62P29, at zoom out
The Red trace is the clock switch control line.
Green and Blue traces are the sampling clock plus and minus lines.
The clock change effect is seen on the green trace.
Figure 1:
Figure 2,3 describe a zoom in of the 200MHz plus and minus LVPECL clock from CDCE to ADS62P29
Trace colors are the same as in figure 1.
It can be seen – cross point to cross point – that the frequency of the clock managed to keep its nominal value after the clock switch. The frequency change is quite minor.
Common mode : although the common voltage changes, the symmetry is kept.
Figure 2 :
Figure 3:
Figure 4 describes the ADC output clock to the FPGA.
Green and blue traces describe ADS62P29 output clock plus and minus.
Red is the clock switch control
Yellow is the 10MHz reference input to CDCE.
The zoom in is taken after clock switch has occurred.
The markers show a cross to cross frequency event of 500MHz ( while the FPGA is designed to handle 400MHz nominal DDR clock and is not designed to tolerate such absolute high frequency and such frequency deviation of ~25%)
Figure 4:
When the system is after or before the the transition between the clk sources the system works correctly. The transition introduces the error in the missing detection of the ADC output clk by the FPGA which results in data errors.
Questions :
- Can TI explain what is the reason of the “high frequency “ at ADS62P29 clock out pins?
- What is the expected behavior of the CDCE during clock switch ? Please note the clock switch is done externally to the CDCE and the failsafe bit is set. There is a period of ~170nSec in which the input to the CDCE is not defined before “new clock” is available.
Thank you
