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ADS54J60: SYNCB Signal

Kyung Whan Yeom
Prodigy 90 points

Part Number: ADS54J60
Other Parts Discussed in Thread: LMK04828,

Hi

I am programing the FPGA for ADC  ADS54J60. In its datasheet, the SYNCB signal of ADS54J60 should change high-low -high. The xilinx jesd204 IP provides the step SYNCB signal which changes from low to high. During the low state of SYNCB, ADC sends K28.5 signal for recovery. I  am curious the step SYNCB signal  is OK for ADS54J60. 

Another question is for ADS54J60EVM. The ADS54J60EVM has two ADCs and LMK04828 for clock signal. My application needs two ADS54J60EVMs. When I use two ADS54J60EVMs, how to sync the sysref clock and refclk of the two ADS54J60EVMs?

Thank you in advance  

  • 0
    TI__Expert 5660 points

    Hi,

     

    Thank you for choosing TI High Speed Converter products. I am sorry to inform that our applications team for high speed data converters does not have the bandwidth available to support University inquiries at this time. If resource bandwidth becomes available, we will follow up with this question.

     

     

    Regards,

    Geoff