ADS131M08: ADS131M08 ADC2 Desynchronization at Exactly 60 Seconds - Multiple Device Configuration (As per datasheet Section 9.1.5)

Hi Ramakrishna Panda,

Please see the feedback below:

1. The section 9.1.5 states that the SYNC/RESET pins must be strobed simultaneously at least one time to align the sample periods internally between devices.
2. There is no additional time needed except tREGACQ minimum 5µs after SYNC/RESET is brought high or for the DRDY rising edge before communicating with the device. The host must wait for tREGACQ before communicating with the device to ensure the registers have assumed their default settings.
3. There is no timeout/counter for this purpose.
4. When multiple ADS131M08 devices are used, all of them should be synchronized at least once after power up. You can configure the registers on the devices first, then synchronize them before collect the data. Depending on your system and clock, periodic synchronization may be needed.

Please notice that the falling edge of /DRDY indicates that the new data is ready, so I would suggest you to check the falling edge instead of the rising edge of /DRDY.

BR,

Dale

Hello Dale,

Thank you for the confirmation.
We have implemented the synchronization per your guidance: "configure registers first, then synchronize before collecting data."

However, we need clarification on three critical points for our production implementation:

**QUESTION 1: Synchronization Frequency**

Our implementation:
• Configure both ADCs → Pulse SYNC once → Start continuous sampling at 954 Hz

You stated: "configure the registers first, then synchronize them before collect the data"

**Does this mean:**
A) Synchronize ONCE after configuration, then collect data continuously?
OR
B) Synchronize before EVERY data collection cycle?
OR
C) Synchronize periodically during continuous operation?

**Follow-up:** After initial SYNC, can we run continuously for hours without re-sync?

**QUESTION 2: DRDY Pin Configuration (Section 9.1.5)**

Per datasheet multiple device configuration:
• ADC1 DRDY → Connected to MCU (interrupt on falling edge)
• ADC2 DRDY → Floating (not connected)

Both ADCs share: CLKIN, SYNC/RESET, SPI bus (separate CS)

Is this correct?

☐ YES - Monitor ADC1 DRDY only, both ADCs synchronized
☐ NO - Must monitor both DRDY pins

**If YES:** Can we read ADC2 data when ADC1 DRDY falls (assuming proper sync)?

**QUESTION 3: When is Periodic Synchronization Needed?**

You mentioned: "Depending on your system and clock, periodic synchronization may be needed."

**Our system:**
• CLKIN: 7.81 MHz (MCU PLL, shared by both ADCs)
• OSR: 4096, Sample Rate: 954 Hz
• Trace length difference: < 2 cm
• Application: 24/7 continuous power metering

**Please advise:**
☐ Periodic sync NOT needed - initial sync sufficient for our configuration
☐ if Periodic sync NEEDED - Recommended interval: __________

**What triggers need for periodic sync?**
• Clock jitter level?
• Temperature variation?
• Time/sample count?
• External vs crystal clock?

**How to detect loss of sync** (without scope)?
• Status register bit?
• Any error indication?

**ADDITIONAL INFO: Our 60-Second Issue**

**OUR INIT SEQUENCE:**

```
1. Power-up both ADCs
2. Assert SYNC low (1ms) → De-assert high → Wait 1ms (tREGACQ)
3. Configure ADC1 registers (MODE, CLOCK)
4. Configure ADC2 registers (MODE, CLOCK)
5. Wait 10ms → Assert SYNC (1ms) → De-assert → Wait 1ms
6. Monitor ADC1 DRDY falling edge
7. Collect data from both ADCs continuously

Is this correct?

Your clarification on these three points is critical for our production design. We need definitive answers to ensure reliable 24/7 operation.

Thank you for your support.

Best regards,
Ramakrishna Panda

Hi Ramakrishna Panda,

Answer 1: For A) and C) options, it really depends on the clock in your system and acceptable error, you can determine it based on your test and system requirements (acceptable mismatch). I do not think you need the option B).

Answer 2: The datasheet already states "Monitoring the DRDY output of only one of the devices is sufficient because all devices convert simultaneously." You can read ADC2 data when ADC1 /DRDY is low. However, you can monitor both /DRDY signals if you want.

Answer 3: See answer 1. Both options were used by different customers. If the accumulated mismatch or error is not acceptable, periodic synchronization is needed. All of them you listed can cause the mismatch (loss of synchronization). There is no status register or bit to indicate the mismatch, however you can see the increased error if you measure the phase difference between devices/channels. Measuring the phase difference is a kay reason to synchronize the ADS131M08 ADCs.

Your sequence looks good to me. Before collecting the data, you can lock the interface by sending the LOCK command, preventing the device from accidentally latching unwanted commands that can change the state of the device.

BR,

Dale