Part Number: ADS62P49
Other Parts Discussed in Thread: CDCE72010,
Dear Sir,
I have made a vivado design on Carrier card Zynq ZC702 and Evaluation board: FMC150 that houses ADS62P49 + CDCE72010. I am uploading my design. The design composes of fmc150_adc_interface module that writes ISERDES2, with all lane mappings and constrainsts as per details provided by the daughter board(FMC150). The part where I am fix is that I need to configure the ADC via PS7/EMIO/SPI0. Now daughter card is having a specific problem, that. It doesn't have Chip Select Pin. It has ADS_SDO and CDCE_SDO pins available. apart from other pins like ADC_n_EN, ADC_RESET, TXENABLE & CDCE_N_EN, CDCE_RESET, CDCE_PD. SO leaving both the SDO_pins, the other 6 pins, as I mentioned, I am driving them through an AXI_GPIO_0. Also using the CDCE_N_EN bit from this GPIO (by slicing) I am driving a mux, that outputs to SPI0_MISO_I. SO selection is done via this. Now the problem is that ADS62P49 & CDCE72010 configurations are not sure to me, as when I try to set reg "0x25 to 1" for ramp. The outputs I get even after bitslip applied(by another axi_gpio_1), are not correct.
So, if you can help me to chalk out 1. Selection of ADS and CDCE chips, 2. then configuring them respectively, 3). then Verification that what I have written to the registers is OK, is needed and I will be highly grateful. The code is written in C through Vitis SDK provided alongwith Vivado 2021.2. I hope I made myself clear. I will upload 1. my Block design and 2. XDC( if 2 files are allowed to drop). If you require the design files, further then I will provide, instantly.
Regards
Abhiram Tripathifmc150_adc_design.pdf