AFE58JD32: ADC Clock Input (ADC_CLK) Minimum Vpp for LVDS

Miles Ransaw

Part Number: AFE58JD32

The AFE58JD32 datasheet specifies a minimum 0.7Vpp for the differential clock amplitude, but most LVDS drivers have 0.35Vpp differential output. Will an LVDS driver with a minimum differential output voltage of 0.35Vpp be sufficient to drive the ADC_CLK input of the AFE58JD32?

2 months ago

+1 Sheetal Gupta 2 months ago

TI__Intellectual 1080 points

Hi Miles,

Typical LVDS differential output (VOUTP-VOUTM) swings 0.7Vpp according to the standard. 350mVpp is the differential swing on VOUTP and VOUTM alone. Overall differential swing will be 0.7Vpp. So, there shouldn't be any problem with respect to clock input.

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AFE58JD32: ADC Clock Input (ADC_CLK) Minimum Vpp for LVDS