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ADS54J60: TI204C-IP V1.12: Applying configuration both ADS54J60 and DAC37J84 using same QUAD GTH 8b10b XCVR

Erivelton Castro
Prodigy 170 points

Part Number: ADS54J60
Other Parts Discussed in Thread: LMK04828, , DAC37J84

Hi,

In my project, I'm using the ADS54J60 and DAC37J84 with my Xilinx Project 11EG FPGA. In this case, I'm using the same GTH DUAL QUAD bank (225 and 226) with QPLL0 for the TX channel (DAC) and QPLL1 for the RX channel (ADS), totaling 8 transmission lanes and 8 reception lanes in the same GTH bank. I'm configuring the DAC's LMFS as 8411 and the ADS's LMFS as 8224. I would like to configure different sampling rates for the DAC and the ADS. I'm using the LMK04828 with one channel to generate the reference clock and the Sysref clock for the DAC, and another channel for the ADS. There's also another channel on the LMK04828 to generate the clock for the DAC's logic core and another channel for the ADS's logic core.

It is possible to use other LMFSvalues ​​for DAC and ADS, such as: LMFS=4421 for DAC and LMFS=4211 or LMFS=4244.

My questions are: 

  1. Can I configure jesd parameters with different LMFS for ADC and ADS on the TI204C without getting an encrypted envelope error?
  2. Can I configure GTH transceiver IP with different QPLL and sampling rate for Tx and Rx?
  3. Can I use the same GTH QUAD BANK for ADC and ADS? Do I need to specifically configure GTH QUAD BANK for DAC (eg. Banb 225 adn 226) and other GTH QUAD BANK for ADS (eg. 227 and 228).
  4. What are the limitations of TI204C version V1.12 for this project?
  5. What are case can be generate encrypted envelope error?

Best Regards,

Erivelton Castro

  • 0
    TI__Intellectual 2550 points

    Hi Erivelton,

    The answer to all of your questions (except for the last one about other LMFS values) is yes. In the TI204c JESD IP, the ADC and DAC link paths are completely independent. Please ensure that the transceiver wrapper is edited to correctly connect the reference clocks, PLLs, pll locked signals, etc.

    Our recommendation is to create separate JESD IP's for separate LMFS values. It is possible to create only one 8 lane and use it for multiple LMFS (where L=8 or L=4), but this is something we have not regressed/validated. If you take this approach, you will need to use the lane_enable signals to ensure that the unused lanes are disabled.

    Regards,
    Ameet