Part Number: DAC8775
Other Parts Discussed in Thread: ADS8688
Hi!
I have designed a PCB (which is now being manufactured) that includes a couple of DAC8775 and also two ADS8688. These devices should share the SPI bus (SDO, SDI, SCLK). However, I'm not sure if these devices will be compatible regarding their SLCK idle mode.
In the ADS8688 datasheet, I can clearly see SLCK should be low when CS is high:
However, it's not as clear in the DAC8775 datasheet. In fact, it seems to suggest SCLK should be high when CS is high:
When sync is high, SCLK is shown both high and pulsing. Does this mean it can also be low?
I'll gladly clarify or add more info about my design if necessary. Thanks!
