what source the DAC_CLK is derived when no clock is connected to pins 8 & 9 (CLKINP/N) of the AFE7225

Hi,

The pin definition of 8/9 in AFE7225 is a main clock input which is used for sampling processing of ADC & DAC. Without providing this clock with AFE7225, it will not work.

Regarding pin 33/34, this is "LVDS bit clock input" for latching data from FPGA. AFE7225 is supposed to get this clock from FPGA and its frequency depends on 1wire, 2wire SDR or 2wire DDR. If you use 2wire SDR interface, your FPAG has to provide AFE7225 with x6 of pattern word rate. If you use 2wire DDR, it'll be 3 times of pattern word rate. And this LVDS bit clock has to be data center aligned from FPGA.

In 2wire SDR mode, the maximum word rate is 65Msps and 125Msps in 2wire DDR mode. As your DAC processing is based on 120MHz, our suggestion is to use 2wire DDR mode. The frame clock input, pin 30/31, is the same rate as word rate.

Thanks,

KW

Hi KW Nam

Thanks

But

again

I want understand from what source the DAC_CLK is derived when no clock is connected to pins 8 & 9 (CLKINP/N) of the AFE7225 

 while there is a clock in the LVDS CLOCK INPUT :  DAC_DCLKINP/N (pins: 33 & 34) as well as Frame clock : " DAC_FCLKINP/N" ( at pins : 30 $ 31)

Is there an inner DAC_CLK source?

Is it is deriver form  LVDS DAC_FCLKINP/N INPUTs ?

Thanks Ezer

Hi, Ezer

DAC_DCLKIN (Pin 33/34) usually comes from FPGA along with LVDS data. CLKIN (Pin 3/4) is required for DAC/ADC sampling processing and there is no inner DAC_CLK source in AFE7225.

Thanks,

KW