Questions about AFE5804

Ren Tong

Other Parts Discussed in Thread: AFE5804

Hi,

Now I am using AFE5804 to design a ultrasound system. Xilinx FPGA is used to control the AFE5804 and deserdes the LVDS signal.

I wonder if anyone here used to design AFE5804 through FPGA. The problem I face now is how to initial the register of AFE5804 correctly . With my code , the data from LVDS is not stable . While power on , it maybe right or not . I doubt there must be something wrong with the initial code. For pressing the reset button , sometimes it can work well through it doesn't work once power on . Additional , My PCB board can't reset itself once power on . The attachment is my initial code of AFE5804.

Any help will be appreciate . Thanks!

over 12 years ago

0 Chuck Smyth over 12 years ago

TI__Expert 6320 points

Ren,

I can't see your attachment, but maybe you can tell me what steps you take to initialize the AFE5804. Also, see page 30 of the datasheet, especially the register initialization steps. Are you doing this?

Thanks,

Chuck Smyth

0 Ren Tong over 12 years ago in reply to Chuck Smyth

Prodigy 30 points

Chuck Smyth,

First of all , thanks for your reply.

For my PCB hardware can't reset the register of AFE5804 , in my program , the first step is using the serial interface, set the S_RST bit high , then reset the S_RST in my code . Then , the other registers are being written by serial interface . And now the phenomenon is the program couldn't work well at the start of power on . But if I press a button at the PCB board which can applying a low-going pulse on the ADS_RESET pin , the program can work well . Is there something wrong with my initial code of AFE5804 ? This program is still making me feel confused. The attachment is my initial code of AFE5804.

Any help will be very appreciated.

6710.AFE_INIT.txt

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:22:41 10/25/2011 
// Design Name: 
// Module Name:    AFE_init_tongren 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module AFE_init(
uclk,
rst,
sdata,
cs,
sclk,
clkp,
clkn
    );
	 
input uclk;
input rst;
output sdata;
output sclk;
output cs;
output clkp,clkn;


reg sclk=1'b0;
reg sdata=1'b0;;
reg cs=1'b1;
wire clkp,clkn;

reg clk_div1=1'b0;
reg clk_div=1'b0;
reg i;
reg [1:0]m;
reg [3:0]j;
reg [2:0]count;
reg [3:0]counter2=9'b000000000;
reg [8:0]counter1=9'b000000000;



/*
always @(posedge uclk)  // 20Mhz
begin
	clk_div1<=~clk_div1;
end
*/




always @(posedge uclk)   // 10Mhz
begin
	if(i<1'b1)
	begin
		i<=i+1'b1;
	end
	else
	begin
		i<=1'b0;
		clk_div1<=~clk_div1;
	end
end




/*

always @(posedge uclk)   // 5Mhz
begin
	if(m<2'b11)
	begin
		m<=m+2'b1;
	end
	else
	begin
		m<=2'b0;
		clk_div1<=~clk_div1;
	end
end

*/


/*
always @(posedge uclk)   // 1.25Mhz
begin
	if(j<4'b1111)
	begin
		j<=j+4'b1;
	end
	else
	begin
		j<=4'b0000;
		clk_div1<=~clk_div1;
	end
end
*/




OBUFDS #(
.IOSTANDARD("LVDS_25")
)
instance_afeclk(
.O(clkp),
.OB(clkn), 
.I(clk_div1) 
);

always @(posedge uclk)
begin
	if(count<3'b111)
		count<=count+3'b1;
	else
		begin
			count<=3'b0;
			clk_div<=~clk_div;
		end
end 



always @(posedge clk_div)
begin
	if (rst==0)
	begin
		counter1<=0;
		sclk<=1'b0;
	end 
	else if (counter1<376)
	begin
		counter1<=counter1+9'b1;
		sclk<=~sclk;
	end
	else
	begin
		counter1<=376;
		sclk<=1'b1;
	end
		
	case(counter1)
		0: begin cs<=1;sdata<=0; end   // CS=1 ��һ��ʱ�ӿ�ʼͨ��SPIд������
		1: begin cs<=1;sdata<=0; end
		2: begin cs<=1;sdata<=0; end
		3: begin cs<=1;sdata<=0; end
		4: begin cs<=1;sdata<=0; end
		5: begin cs<=1;sdata<=0; end
		6: begin cs<=1;sdata<=0; end
		7: begin cs<=1;sdata<=0; end
		8: begin cs<=1;sdata<=0; end
		9: begin cs<=1;sdata<=0; end
		10: begin cs<=1;sdata<=0; end

/*****************register 0x00--0x000001--0000_0000_0000_0000_0000_0001********/ //software to reset all the register of AFE5804
		57: begin cs<=0;sdata<=1; end
		58: begin cs<=0;sdata<=1; end
		
		
		59: begin cs<=1;sdata<=0; end   //����CS,ֹͣд��
		60: begin cs<=1;sdata<=0; end
		61: begin cs<=1;sdata<=0; end   //����CS,ֹͣд��
		62: begin cs<=1;sdata<=0; end		
		
/*****************register 0x25--0x250010--0010_0101_0000_0000_0100_0000*********/ //  D4=1,LVDS���һ���̶�ֵ �̶������[D11:D10]=00;

		67: begin cs<=0;sdata<=1;end
		68: begin cs<=0;sdata<=1;end
		73: begin cs<=0;sdata<=1;end
		74: begin cs<=0;sdata<=1;end
		77: begin cs<=0;sdata<=1;end
		78: begin cs<=0;sdata<=1;end
		
//		97: begin cs<=0;sdata<=1;end
//		98: begin cs<=0;sdata<=1;end
		
		
		111: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		112: begin cs<=1;sdata<=0;end  
		113: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		114: begin cs<=1;sdata<=0;end
		
/*****************register 0x14--0x1400FF--0001_0100_0000_0000_1111_1111*********/ // [D7:D0]=0xFF,CH1--CH8 ѡ�������ģʽ
		121: begin cs<=0;sdata<=1;end
		122: begin cs<=0;sdata<=1;end
		125: begin cs<=0;sdata<=1;end
		126: begin cs<=0;sdata<=1;end
		147: begin cs<=0;sdata<=1;end
		148: begin cs<=0;sdata<=1;end
		149: begin cs<=0;sdata<=1;end
		150: begin cs<=0;sdata<=1;end
		151: begin cs<=0;sdata<=1;end
		152: begin cs<=0;sdata<=1;end
		153: begin cs<=0;sdata<=1;end
		154: begin cs<=0;sdata<=1;end
		155: begin cs<=0;sdata<=1;end
		156: begin cs<=0;sdata<=1;end
		157: begin cs<=0;sdata<=1;end
		158: begin cs<=0;sdata<=1;end
		159: begin cs<=0;sdata<=1;end
		160: begin cs<=0;sdata<=1;end
		161: begin cs<=0;sdata<=1;end
		162: begin cs<=0;sdata<=1;end
		
		163: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		164: begin cs<=1;sdata<=0;end  
		165: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		166: begin cs<=1;sdata<=0;end


/*****************register 0x12--0x124333--0001_0010_0100_0011_0011_0011*********/ // D14Ĭ��Ϊ1�������ڲ��迹ƥ��
		173: begin cs<=0;sdata<=1;end
		174: begin cs<=0;sdata<=1;end
		179: begin cs<=0;sdata<=1;end
		180: begin cs<=0;sdata<=1;end
		185: begin cs<=0;sdata<=0;end   // �����ڲ��迹ƥ��
		186: begin cs<=0;sdata<=0;end

/*		
		195: begin cs<=0;sdata<=1;end
		196: begin cs<=0;sdata<=1;end
		197: begin cs<=0;sdata<=1;end
		198: begin cs<=0;sdata<=1;end
*/		
		203: begin cs<=0;sdata<=1;end
		204: begin cs<=0;sdata<=1;end
		205: begin cs<=0;sdata<=1;end
		206: begin cs<=0;sdata<=1;end
/*		
		211: begin cs<=0;sdata<=1;end
		212: begin cs<=0;sdata<=1;end
		213: begin cs<=0;sdata<=1;end
		214: begin cs<=0;sdata<=1;end
*/		
		215: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		216: begin cs<=1;sdata<=0;end  
		217: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		218: begin cs<=1;sdata<=0;end

/*****************register 0x11--0x11--0001_0001_0000_0100_0100_0100*********/ // D14Ĭ��Ϊ1�������ڲ��迹ƥ��

		225: begin cs<=0;sdata<=1;end
		226: begin cs<=0;sdata<=1;end
		233: begin cs<=0;sdata<=1;end
		234: begin cs<=0;sdata<=1;end
		
		245: begin cs<=0;sdata<=1;end
		246: begin cs<=0;sdata<=1;end
		
		253: begin cs<=0;sdata<=1;end
		254: begin cs<=0;sdata<=1;end
		
		261: begin cs<=0;sdata<=1;end
		262: begin cs<=0;sdata<=1;end
		
		267: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		268: begin cs<=1;sdata<=0;end  
		269: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		270: begin cs<=1;sdata<=0;end
		

/*****************register 0x26--0x260000--0010_0110_1100_1100_1100_0000*********/ // �̶������[D11:D0]=0x332=12'b0011_0011_0010
/*		275: begin cs<=0;sdata<=1;end
		276: begin cs<=0;sdata<=1;end
		281: begin cs<=0;sdata<=1;end
		282: begin cs<=0;sdata<=1;end
		283: begin cs<=0;sdata<=1;end
		284: begin cs<=0;sdata<=1;end
		
		287: begin cs<=0;sdata<=1;end
		288: begin cs<=0;sdata<=1;end
		289: begin cs<=0;sdata<=1;end
		290: begin cs<=0;sdata<=1;end
		
		295: begin cs<=0;sdata<=1;end
		296: begin cs<=0;sdata<=1;end
		297: begin cs<=0;sdata<=1;end
		298: begin cs<=0;sdata<=1;end
		
		303: begin cs<=0;sdata<=1;end
		304: begin cs<=0;sdata<=1;end
		305: begin cs<=0;sdata<=1;end
		306: begin cs<=0;sdata<=1;end
		
		

		
		319: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		320: begin cs<=1;sdata<=0;end  
		321: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		322: begin cs<=1;sdata<=0;end
*/		
/*****************register 0x45--0x450001--0100_0101_0000_0000_0000_0001*********/ // [D1:D0]�ֱ�Ϊ��ͬ�����
      273: begin cs<=0;sdata<=1;end
		274: begin cs<=0;sdata<=1;end
		281: begin cs<=0;sdata<=1;end
		282: begin cs<=0;sdata<=1;end
		285: begin cs<=0;sdata<=1;end
		286: begin cs<=0;sdata<=1;end
		 
		315: begin cs<=0;sdata<=1;end 
		316: begin cs<=0;sdata<=1;end
      
		319: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		320: begin cs<=1;sdata<=0;end  
		321: begin cs<=1;sdata<=0;end   // ����CS��ֹͣд��
		322: begin cs<=1;sdata<=0;end
		


/*****************register 0x42--0x4280E5--0100_0010_1000_0000_1110_0101********/ //D15,D7Ĭ����1��D0=1�����ʱ�����룻D2=1,�����ڲ�ʱ��У׼��D3=0??;[D6:D5]=11,���������ʱ����λһ��
		325: begin cs<=0;sdata<=1; end
		326: begin cs<=0;sdata<=1; end
		335: begin cs<=0;sdata<=1; end
		336: begin cs<=0;sdata<=1; end
		339: begin cs<=0;sdata<=1; end
		340: begin cs<=0;sdata<=1; end
		
		355: begin cs<=0;sdata<=1; end
		356: begin cs<=0;sdata<=1; end
		
		357: begin cs<=0;sdata<=1; end
		358: begin cs<=0;sdata<=1; end
		359: begin cs<=0;sdata<=1; end
		360: begin cs<=0;sdata<=1; end
		
		
		
		365: begin cs<=0;sdata<=1; end
		366: begin cs<=0;sdata<=1; end
		369: begin cs<=0;sdata<=1; end
		370: begin cs<=0;sdata<=1; end

		
		371: begin cs<=1;sdata<=0; end   // ����CS��ֹͣд��
		372: begin cs<=1;sdata<=0; end
		373: begin cs<=1;sdata<=0; end
		374: begin cs<=1;sdata<=0; end   // ����CS��ֹͣд��
		375: begin cs<=1;sdata<=0; end
		376: begin cs<=1;sdata<=0; end
		


		
		default : begin cs<=0;sdata<=0;end
	endcase
end 


endmodule


/*****************register 0x00--0x000000*********/ // ��λADC�����λ

/*****************VCA_resigter_design--03��16��17��18****************/

/*****************register 0x03--0x030020*********/ // D5λ ��1��VCA����״̬����λ
/*****************register 0x16--0x16FF1C*********/ // D0,D1ǿ����1��D4λ��1��ѡ��TGC_MODE 1�� D6,D7 �����ڲ�PGA���棬�˴���ʱΪ00������Ϊ20dB.
/*****************register 0x17--0x17FFFF*********/ // ��register 0x16��D8----register 0x18��D7 ΪVCA���濪�ؿ��ƣ��˴�ȫ����1
/*****************register 0x18--0x1800FF*********/ //


/*****************ADC_resigter_design--0F��46****************/

/*****************register 0x0F--0x0F----*********/ // D0--D7ΪƬ��8ͨ��ADC�Ŀ��أ�D8λ��1Ϊ���ֵ��ģʽ��[D10:D9]=01 ��ȫ���ģʽ [D10:D9]=10 ���ֵ��ģʽ
/*****************register 0x46--0x46A200*********/ // D15,D13,D9ǿ����1��D2λΪ�����ʽ���˴���0����ͨ��ʽ�����1Ϊ�����������D3Ϊ���˳�򣬴˴���0��LSB first��D4ΪLVDS���ѡ�񣬴˴���0��DDR��ʽ���



/*****************Program_gain_resigter_design--2A,2B****************/

/*****************register 0x2A--0x2A----*********/ // D15--D0 �ֱ����CH1--CH4����������
/*****************register 0x2B--0x2B----*********/ // D15--D0 �ֱ����CH5--CH8����������


/*****************LVDS_resigter_design--45****************/

/*****************register 0x45--0x0F000X*********/ // [D1:D0]=01 12λADC�̶����010101010101 [D1:D0]=10 12λADC�̶����111111000000