Hello,
I posted this issue quitre a while ago, but with partial test.
Now I have to do full test and found very disappointed response from the device, it gives me totally wrong results, the readings are way different than the input
VREF is tied to 4096 mV for 12-bit ADC, so the read result is supposed to follow the input
Channel 0 |
Channel 1 |
||
Input (mV) |
Read (mV) |
Input (mV) |
Read (mV) |
0 |
1152 |
0 |
96 |
250 |
848 |
500 |
4000 |
500 |
576 |
1000 |
3696 |
750 |
288 |
1500 |
3568 |
1000 |
0 |
2000 |
3504 |
1250 |
3808 |
2500 |
3456 |
1500 |
3520 |
3000 |
3392 |
1750 |
3232 |
3500 |
3328 |
2000 |
2944 |
4000 |
3232 |
2250 |
2624 |
4500 |
4080 |
I'm using
- Manual channel select
- Internal clock
- Auto-trigger
- Disable TAG bit
My procedure is
- Reset the chip with written data 0xE000
- Set config with 0xE4FD, verified by readback with exactly the same data written to ensure the right clock phase and polarity for SPI bus of the chip
I tried to read resulst by 2 ways
1) Using 2 separate operations (each has its own SPI CS)
1a) Write 4 bits of channel number 0 or 1
1b) Write 4 bits of 0xD and read 12 bits of result
2) Using only 1 operation (one SPI CS) with writing first 4 bits of channel number and read 12 bits for result
Both ways give me the same resuls as in the table above
What's wrong with me in reading results ?
Thanks,
~Duy-Ky
Below is a capture of its circuitry