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ADS7230 gives wrong results

Other Parts Discussed in Thread: ADS7230, ADS8332

Hello,

I posted this issue quitre a while ago, but with partial test.

Now I have to do full test and found very disappointed response from the device, it gives me totally wrong results, the readings are way different than the input

 VREF is tied to 4096 mV for 12-bit ADC, so the read result is supposed to follow the input

Channel 0

Channel 1

Input (mV)

Read (mV)

Input (mV)

Read (mV)

0

1152

0

96

250

848

500

4000

500

576

1000

3696

750

288

1500

3568

1000

0

2000

3504

1250

3808

2500

3456

1500

3520

3000

3392

1750

3232

3500

3328

2000

2944

4000

3232

2250

2624

4500

4080

 

I'm using

  • Manual channel select
  • Internal clock
  • Auto-trigger
  • Disable TAG bit

My procedure is

  1. Reset the chip with written data 0xE000
  2. Set config with 0xE4FD, verified by readback with exactly the same data written to ensure the right clock phase and polarity for SPI bus of the chip

I tried to read resulst by 2 ways

1) Using 2 separate operations (each has its own SPI CS)

   1a) Write 4 bits of channel number 0 or 1

   1b) Write 4 bits of 0xD and read 12 bits of result

2) Using only 1 operation (one SPI CS) with writing first 4 bits of channel number and read 12 bits for result

Both ways give me the same resuls as in the table above

What's wrong with me in reading results ?

Thanks,

~Duy-Ky

Below is a capture of its circuitry

  • Hi Duy-Ky,

    The capture that you provided for the circuitry of the ADS7230 is not visible for some reason on your post, can please attach another copy of it so that I may reveiw how you are driving the converter? I would also like to see what kind of LPF you have on the front end of the device as this may add to some of your troubles.

    Also, can you please provide me with a scope capture of your DOUT, SCLK, and FS/CS so that we may verify that you are reading off the right critical edge for this part? From reveiwing the data sheet (page 13, Figure 3. Timing for Conversion and Acquisition Cycles for Autotrigger (Read While Converting)) it appears that while operating in the auto trigger mode that the critical edge would be the falling edge of the FS/CS. Is this how you are operating?

    Regards,

    Michael

  • Hi Michael,

    Attached is PDF file with waveform capture in writing and reading CFR with config data 0x4FD and circuitry of the chip

    Thanks,

    ~Duy-Ky

    8686.ADC ADS7230 Test Results 02.pdf

  • Hi Duy-ku,

    Take a look at this post -

    http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/150096.aspx#545876

    I am fairly certain that the ADS7230 shares the same digital core as the ADS8332 so the same operating conditions hold true. I would trying either using auto trigger auto channel mode or manual trigger manual channel mode to see if you start seeing the correct results.

    Regards,

    Tony Calabria