Need some verification, the datasheet is no quite clear.
According to the datasheet, the Dataout to Outclk setup and hold has a guaranteed minimum of 1 ns when operating at 160 MHz. The datasheet also notes that "This parameter is a function of the CLK frequency - increasing directly as the frequency is lowered" (note 10). The output is going to an FPGA and we need to know what this means if operating at 112 MHz. It sounds like we'd have a Tsu = 1.67 ns and Th = 1.67 ns, but it would be nice to get some confirmation that the setup and hold times are symmetrical, and that they don't shift in some other way as the clock frequency is lowered, i.e. it looks like the clock is centered in the data, we just need to know what the Tsu and Th minimums would be with a 112 MHz clock.
