• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Subscribers 48 subscribers
  • Views 3009 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8330 in Manual Mode

Fabian Braun
Prodigy 80 points
Other Parts Discussed in Thread: ADS8330, TMS320C6416

Hi,

I am using the ADS8330 ADC connected to an AVR microcontroller via SPI bus. (Bus Clock so far 2 MHz, to be increased maybe later).
I have set the ADC to interal clock, manual trigger, and manual channel select, Pin 10 has INT function and is active low. Tag mode is disabled.
The following sequence is used to read out the ADC values:

1. ADC_Init() -> perform ADC reset (via CFR), set CFR to default, configure CFR as described above
2. Reading out ADC Value by:
   a) first writing the command to select which channel to read (CH0 or CH1)
   b) then i set the CONVST pin low
   c) then i wait until INT pin is pulled low by the ADC or a timeout (of 10 milliseconds) occured
   d) afterwards i set CONVST pin high
   e) and read out the ADC value by simply sending 0x0D00 (read data command) over the SPI and in the same time reading the 16bit received from the ADC
(of course CS is pulled low every time SPI data is transferred)

The problem is: for every second readout the INT pin of the ADC isn't pulled low, which means to me that there hasn't been any conversion and my routine fails with a timeout. (The only thing happening to the ADC between every second readout is therefore only the channel select command and the CONVST pin which is pulled low for about 1 ms. I've also tried it without the channel select command, with the same result).
For now i have implemented a dummy read such that i can easily interface the ADC, but that can't be the solution and furthermore it steals me time.
What could be wrong?

In manual mode: do I have to select the input channel every time before performing a sample or is this only necessary once and for the rest of the time the mux is switched to this channel and all the following samples origin from the lastly selected channel?
Is this the same for the auto trigger mode? Once at the beginning you select/switch the channel and then all the samples are from the same channel?

Furthermore I do have a question regarding the auto mode (auto trigger):
Unfortunately my microcontroller is a bit too slow to be able to read out a sample with a rate of around 1MHz.
What happens if data is available and it takes me too long to read it out such that the ADC would've sampled already the next sample. Is the sample being overwritten or does the ADC halt the conversion until the last sampled value is transferred over SPI?

Thank you very much for your help in advance!

Best regards,
Fabian

PS: If there could be some useful (example) code for the ADS8330 around I would be grateful if you could provide me with this...

  • 0
    TI__Mastermind 46290 points

    Fabian,

    Welcome to the precision data converters forum, I'm currently traveling but I should be able to look into this properly on Friday when I return to my lab. Thanks for your patience.

  • 0 in reply to Kevin Duke
    Prodigy 80 points

    Hi Kevin,

    Thanks a lot for your quick response!

    I do have another - rather urgent question - which I think you might be able to answer right away.
    (Today I implemented DMA access to the ADC, since it was not supported by the current SPI module i had to switch to the USART-SPI module, where I stumbled over a huge problem)
    I've set up the SPI clock polarization for sampling/data valid on falling edge as stated in the datasheet:

    ADS8330 Datasheet said:
    
Output data are valid at the falling edge of SCLK with td(SCLKF-SDOVALID) delay so that the host processor can read it at the falling edge. Serial data input is also read at the falling edge of SCLK

    But look at my scope outputs, especially "DSC00456_writeCFR_Reset.JPG", where it's nicely visible thanks to vertical cursors…
    The channel configuration is as follows: (CH1 - SDI (MOSI); CH2 - SCLK; CH3 - ADC_CS; CH4 - SDO (MISO)):
    The SDI (MOSI) pin is clearly set and not changing during the falling edge, but the answer from the ADS8330at SDO (MISO) is changing exactly during the falling edge of SCLK. (I know my clock frequency is rather low, but this also happens for 2 or 16 MHz SCLKs - it's just that there my lines have lots of overshoots - another problem to solve ...)


    I'm almost sure it's me who's doing a huge mistake. But what?

    Thanks a lot for your help in advance!

    Regards, Fabian

    PS: I do have troubles uploading pictures, you can get them here:

    http://people.ee.ethz.ch/~fbraun/adc/DSC00453_readCFR.JPG
    http://people.ee.ethz.ch/~fbraun/adc/DSC00454_defaultCFR.JPG
    http://people.ee.ethz.ch/~fbraun/adc/DSC00455_readCFR2.JPG
    http://people.ee.ethz.ch/~fbraun/adc/DSC00456_writeCFR_Reset.JPG

  • 0 in reply to Fabian Braun
    TI__Mastermind 46290 points

    Fabian,

    Do you have a schematic for this? What are your supply voltages? Depending on the configuration of your supplies the hold times on SDO are pretty short - between 2 and 7.5ns, a closer view of "DSC00453_readCFR.JPG" at the clock edge would be helpful, since as you mentioned the clock frequency of your current set up is pretty slow.

    Overshoot problems are usually pretty easy to address, you can add some resistance and capacitance to try to filter out the high frequency components (i.e. impulses), this should smooth out your edges. Be careful not to apply this too liberally though and render the digital lines useless.

    I do not have any ADS8330s handy right now. I should have something to work with next week to investigate your other concerns.

  • 0 in reply to Kevin Duke
    TI__Mastermind 46290 points

    Also, if you can adjust the drive strength of your digital signals you should see some of the overshoot issues go away.

  • 0
    TI__Mastermind 46290 points

    Fabian,

    Fabian Braun said:
    I am using the ADS8330 ADC connected to an AVR microcontroller via SPI bus. (Bus Clock so far 2 MHz, to be increased maybe later).
    I have set the ADC to interal clock, manual trigger, and manual channel select, Pin 10 has INT function and is active low. Tag mode is disabled.
    The following sequence is used to read out the ADC values:

    Can you share a scope capture of you writing and reading this desired configuration on the bus? The screen shots you've shared of reading the CFR register seem to be with the defaults contents. I'd like to verify that we are operating in the configuration we think we are...

    Fabian Braun said:
    In manual mode: do I have to select the input channel every time before performing a sample or is this only necessary once and for the rest of the time the mux is switched to this channel and all the following samples origin from the lastly selected channel?
    Is this the same for the auto trigger mode? Once at the beginning you select/switch the channel and then all the samples are from the same channel?

    You only need to set the MUX once in manual channel select mode. Auto-trigger & manual channel selection is not a fully supported mode for the ADS8330, the PDS should be updated soon to reflect this. In this case the device does not respond to a request to change channels since it is, more or less, constantly converting and from the outside you have no way to tell when the device isn't converting. You could switch from auto-trigger to manual trigger mode briefly, reset the MUX, and then re-enter auto-trigger mode with the channels now changed. Otherwise in auto-trigger manual-channel select you will get results from a single channel.

    Fabian Braun said:
    Furthermore I do have a question regarding the auto mode (auto trigger):
    Unfortunately my microcontroller is a bit too slow to be able to read out a sample with a rate of around 1MHz.
    What happens if data is available and it takes me too long to read it out such that the ADC would've sampled already the next sample. Is the sample being overwritten or does the ADC halt the conversion until the last sampled value is transferred over SPI?

    Generally the sample is overwritten and the result over the SPI bus is corrupted. I haven't confirmed that with the ADS8330 specifically yet, though. 

    Fabian Braun said:
    PS: If there could be some useful (example) code for the ADS8330 around I would be grateful if you could provide me with this...

  • 0 in reply to Kevin Duke
    Prodigy 80 points

    Kevin,

    The ADC/DAC part of my schematic you can see here: http://people.ee.ethz.ch/~fbraun/adc/SchematicSnapshot.png
    I'm working with 3.3V. The digital lines are all directly connected to the AVR Microcontroller...unfortunately without Series Resistors in the lines nor Capacitors to GND for the moment.
    I was able to set a slew rate limitation (the only drive strength limitation I can adjust) for the I/O pins of the SPI which reduced the overshoot but only slightly. I've tried with a 50 Ohm series resistance in the SCLK line (without an external capacitance) this helped much more but still wasn't totally satisfying.
    What procedure would you suggest to determine the optimal values of the series Rs and Cs? Just try and see? :)

    The SCLK timing now makes sense after your explanation and another thourough reading of the datasheet. It was just weird because most of the SPI devices i was working with so far seemed to have the SDO output rather shifted by half a SCLK period (to the right on the scope picture) such that the SDO output is for sure totally stable at the falling edge and not changing some nanoseconds afterwards.
    (as briefly sketched in: http://people.ee.ethz.ch/~fbraun/adc/DSC00456_writeCFR_Reset_Expected.png)
    But since the ADC is designed for 1MHz sampling rate and therefore much faster SPI clocks it makes sense. I've just used a very low SPI frequency to ensure I don't have any troulbes due to my overshoots. (But it turned out to be a bad idea ...)
    I now set the SPI clock to 16Mhz - unfortunately still with quite some overshoots - but at least the ADC data i read out is valid and I can easily read out 100 (or more) consecutive samples via DMA.
    So the SPI clock issue is resolved!

    Furthermore the problem (every second reading zero or INT not going low after CONVST toggle) mentioned at the beginning doesn't occur anymore when I use the ADC triggered with 50kHz sampling rate and constantly read out the data via DMA.
    But if I read it with the original method with lots of delays and polling I still have the problem that every 2nd readout is zero or better said that the ADC doesn't respond with an INT.
    This doesn't really bother me. The important thing is that the ADC works correctly in DMA mode! So problem "solved" as well. Even though I don't understand the reason...

    The only remaining thing is then to properly tune the Rs/Cs to reduce the overshoots...

    Thank you very much for your help!

    Regards,
    Fabian

  • 0 in reply to Kevin Duke
    Prodigy 80 points

    Hi Kevin,

    Thank you very much for your answers. As already mentioned in my last post - which we must've been writing at the same time :) - my ADC now works in manual channel select and manual trigger mode when using a CONVST pulse frequency (=sampling frequency) of about 50kHz and reading out the data constantly via DMA at a SPI frequency of ~16MHz.

    Kevin Duke said:
    Can you share a scope capture of you writing and reading this desired configuration on the bus? The screen shots you've shared of reading the CFR register seem to be with the defaults contents. I'd like to verify that we are operating in the configuration we think we are...


    Yes you're right. I'm sorry for the confusion...This were just some default settings I've tried to ensure/verify the SCLK edge "problem".
    My project is in the very last phase/days...therefore my time is rather limited. If i find some time i'll shoot some more screenshots with my scope and post them, ok?

    Thanks again!
    Regards,
    Fabian

  • 0 in reply to Fabian Braun
    TI__Mastermind 46290 points

    Fabian,

    Check out this presentation from a colleague for more information on fixing the ringing issue. 

    4812.transmissionlines.ppt

  • 0 in reply to Kevin Duke
    Prodigy 80 points

    Perfect! Thanks a lot Kevin, that's exactly what I was looking for...

    Best regards from Switzerland,
    Fabian

  • 0 in reply to Fabian Braun
    Prodigy 40 points

    hello Fabian hello ti,

    from sudi

    please help me to solve the final problem of my project

    i am using the ADS8330 to get ADC samples on both channels i have configured the ADC in Manual channel select ,Internal clock,Manual Trigger

    the program flow is as like

    1.Select the First Channel to read

    2.Give the CONVST SIGNAL

    3.CS to low

    4.Wait for 2msec

    5.give the Read command

    4.wait for 2msec

    5.Read the data

    6.Remove the CONVST Signal

    7.CS to high

    8. Select the Second channel to read

    9.Repeat the steps from the 2 to 8

    til now i tested that its working for the individual channels

    but while attempting for the second channel data its giving the data of the first channel itself

    If i make the channel 0 GND then the second channel data is also taking GND even if its maintained with some voltage.

    ans also TI may suggest that to use the Auto channel select and auto trigger

    see as i am using the spi comn, i dont have the control over the SCLK (WHICH IN TURN CCLK FOR THE ADC)

    and also for the Auto channel select i need to enable the TAG bit but i cant read the TAG bit value on the SPI data in as its max register storage will be for the 16 bit only

    So any how i need to go with the MAnual Channel Select , internal clock ,Manual trigger

    If its thing how to solve this problem as i have tried with so many techinques but no result

    whether i need to change the IC itself

    Please help me