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Other Parts Discussed in Thread: ADS5545, ADS6149

Hello all,

I am using the ADS5545 ADC in a design with a Virtex 5 FPGA..  We are using the 5545evm evaluation module ( for testing.  I notice that board has a Spartan3 FPGA on it.  This means that there must be Xilinx-compatible interface code in the design.  I am interested in getting this code so that we may handily use the device in our new design with as little new code as possible.  I have contacted TI directly and submitted a web case and have gotten very little response in a matter of weeks.



Northrop Grumman Corporation

  • Hi,

    Your request for the FPGA code came in to us through our Product Information Center yesterday, and I replied through that channel already so you should be getting closure from that direction shortly.

    We do not have FPGA code for the Virtex 5.  What we *do* have, and supply when requested, is the *Verilog* source code for the Virtex 4 that is on the TSW1200.  The Virtex 4 code could be used as a starting point, as the primary Xilinx cells that we use to latch the data into the Virtex4 and meet timing are also available on the Virtex 5.  The TSW1200 Virtex 4 uses the IDDR cell to latch in the DDR LVDS, and uses the IDELAY cell with an appropriate default tap setting to meet timing into the IDDR cell.  Both these cells are available in Virtex 5, but the necessary default tap setting would likely be different.

    The ADS5545 EVM that you reference is an older revision of the EVM, ad the current revision of the EVM for that ADC does not have the Xilinx FPGA on board anymore.  At the time of the release of the first ADS5545 EVM, we had available the TSW1100 Cpature Card which could be used in place of a logic analyzer to capture the digital samples from the EVM and upload the sample data to a PC.  The TSW1100 was made to conect to our ADC EVMs that had a CMOS interface.  Later we released the TSW1200 to do the same function with ADC EVMs that have an LVDS interface.   The Xilinx Spartan FPGA that was on the original ADS5545 EVM simply converted the DDR LVDS to CMOS.  As such that code would not likely be of much use.  In addition, I believe that FPGA was not even designed with RTL code at all, but rather designed schematically.  As I said, it is an old design, but there may still be some of those versions in stock.  The new revision of EVM for that device shares the underlying circuit board with the ADS6149 EVM and now connects with the TSW1200 or TSW1400.  The TSW1200 code would be the closest to what you are looking for.



    Richard P.

  • Thank you Richard.  I also got a helpful response from James Rose in my email.  I have the reference code now. 

    Now I am also wondering if a VHDL model exists for the ADS5545 hardware so that it can be plugged into my simulation.