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ADC8D1500 Questions - LVDS Question

Other Parts Discussed in Thread: ADC08D1500, LMK04031, LMK04001, LMK04011


There are  two voltage levels available, assume for example they are  using the higher voltage setting.  In the digital output characteristics section, the data sheet quotes a nominal differential output voltage of 710mV, with a range of 400mV to 920mV.  Yet in section 1.1.6, it quotes a nominal output current of 3.0mA into a 100 ohm termination, for a 300mV differential output.  It also quotes a short circuit current of 4mA, indicating a maximum voltage across the termination resistor of 400mV.  It’s worth noting that for LVDS, 300mV is a standard output. Can you resolve this contradiction?

Is there a way to determine the output jitter on the DCLK in DDR mode? 



  • Hi Anish

    The voltage levels described in the ADC08D1500 datasheet output characteristics table are specified in  "mV peak to peak". The typical value is 710mVp-p when OutV=Va and 510mVp-p when OutV=GND.

    The text in section 1.1.6 describes the voltage across a 100 ohm termination being 300 mV differential (peak rather than peak to peak) when a nominal 3 mA current is sourced by the LVDS output drive of the ADC.

    The numbers in the output characteristics table are the more accurate ones that should be used. Based on the 710mVp-p output (355mV peak) the typical output current in this mode is 3.55 mA rather than the 3mA described in section 1.1.6. The specified max current would be 920mV/100ohms/2 = 4.6mA while the minimum would be 400mV/100ohms/2 = 2mA. I hope this clears up the contradiction that you saw then reviewing the information.

    We do not have a specification for additive jitter on the DCLK outputs. The jitter is low enough that downstream capture devices like FPGAs or ASICs will reliably capture the output data. We do not recommend using the DCLK as a precision timing output for other purposes. If a high quality clock at a fraction of the ADC clock frequency is required I would recommend using a product like the LMK04001, LMK04011 or LMK04031 to provide both the ADC and sub-harmonic clocks.

    Best regards,

    Jim B

  • I’m not sure I understand that answer.  The peak to peak voltage should equal the differential voltage, assuming both lines in the pair transition simultaneously, which they should.  The digital output characteristics section also refers to this as “LVDS Differential Output Voltage”, and specifies that it is measured differentially.  Should I interpret this to mean that the actual differential voltages are half the values quoted in the digital output characteristics section?  Where does the factor of 2 come in the specified minimum current equation 400mV/100ohms/2 = 2mA you provided come from?

  • Hi Anish

    I apologize, I know the units used in our GSPS ADC datasheets for LVDS output are somewhat confusing.

    The LVDS outputs can have either a 0 or 1 logic state. In each of these states the output voltage is the "peak" voltage, which is the voltage created by the output current flowing in the termination resistance. The "peak to peak" voltage describes the total variation in output voltage for an output that transitions from a logic 0 to a logic 1, where the direction of the output current changes.

    For a 3.55mA output current the output voltage will be 355mV_peak and 710mV_peak-to-peak.

    You are correct, to translate from our datasheet peak to peak numbers to a conventional LVDS Vod specification requires dividing our numbers by 2.

    I hope this is helpful.

    Best regards,

    Jim B