There are two voltage levels available, assume for example they are using the higher voltage setting. In the digital output characteristics section, the data sheet quotes a nominal differential output voltage of 710mV, with a range of 400mV to 920mV. Yet in section 1.1.6, it quotes a nominal output current of 3.0mA into a 100 ohm termination, for a 300mV differential output. It also quotes a short circuit current of 4mA, indicating a maximum voltage across the termination resistor of 400mV. It’s worth noting that for LVDS, 300mV is a standard output. Can you resolve this contradiction?
Is there a way to determine the output jitter on the DCLK in DDR mode?