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DAC8832 Major-Carry Glitch

Other Parts Discussed in Thread: OPA2209, OPA735, OPA727, OPA277, OPA704, DAC8562, DAC8832

Hi @all,

I'm using the DAC in a high-speed control loop.

Refering to the data-sheep, p.11, I expected a glitch-amplitude of about 20mV.

What I see now, is a glitch of about 250mV (code change from 7fff <> 8000), tau is about 400ns.

Can this be true ?

Rgds

Martin

  • Hi Martin,

    Can you share a schematic with us? 

  • Hi Kevin,

    sure you can get one...

    Supply is 5V, Ref is 4.096V, buffered by an OP2209.

    The Glitch is measured at Pin2 (Vout), same result if the following OpAmp is unpopulated.

    All signals (Vcc,Ref) are clean, the "static" behaviour of the DAC is as expected.

    Martin

  • Martin,

    Thanks for the details. I'm going to assume OP2209 is really OPA2209.

    If you can post an oscilloscope capture of the glitch happening in your system that could be helpful, but I can go ahead and make some guesses at what it looks like. I expect that since the amplitude of the glitch observed in your system is of greater magnitude than the glitch in our datasheet, the duration of your glitch is shorter. To phrase it more precisely, your system exhibits faster settling time than what is illustrated in the datasheet. Settling time vs. glitch amplitude is a 'classic' trade-off in DAC systems - the energy has to go somewhere and you can either choose to have a large short impulse or a long small curve. There are more complex solutions that involve implementing a sort of switch cap circuit that will help achieve fast settling time and small amplitude, but we can discuss that pending your interest.

    The speed of your amplifier is why you see glitch of greater amplitude than is illustrated in the datasheet. On our EVM we use OPA735 with a GBWP of 1.6MHz. The datasheet recommends OPA277, OPA704, or OPA727 - these guys have similar GBWP at ~1MHz. I would assume that one of these devices were used to generate the characterization curves, but I couldn't say for sure which one it was off the top of my head. The OPA2209, however, has a much faster GBWP at 18MHz.

    You've got two easy methods to fix this problem; replace the buffer amplifier with a slower amplifier or add an R/C on the output of your current buffer. The R/C will achieve the same effect.

  • Hi Kevin,

    Thanks for your response.

    You're right -- it is an OPA2209 -- sorry for that typo.

    Scope-plot: I could send you one, but it's not sensational: As I told before, peak-amplitude of 250mV and about 400ns decay-time-constant, so "settling time" is about 2us.

    As I mentioned ealier, this glitch is seen at the Vout-Pin of the DAC and is independend of the type/BW of the following Amp.

    I was not aware, that the plots are showing the behaviour of a circuit but not of the device...

    R/C: I tried that already: an addional 47p from Vout to Gnd lowers the amplitude to about 100mV, with 220p it comes near to 20mV, "settling-time" now is about 6us.

    And as you explained earlier: By that I'm only redistributing the energy in time. The response from my control-path is more or less independend of the amplitude but depends on the total energy...

    So, if I stay with that DAC, I'm afraid, I have to insert a S/H-stage. As my update-rate is about 2MHz (1.92MHz), it seems to become a bit tricky:

    -- even after 400ns, the amplitude is still about 40mV (at Vout-pin)

    -- the output resistance of the dac (6k) limits the hold-capacity to about 10pF, so the switch should have a very low transfer-charge or

    -- I need an addional buffer between DAC and Cap...

    As the very last chance, I could think about lowering the update-rate to 1.5 or even 1MHz, so it would become easier for the S/H-circuit.

    Any more ideas?

    Rgds

    Martin

  • Martin,

    At this particular moment, actually seeing the real schematic would answer a few questions I have rather than hearing the schematic in words. Especially where you've placed these R/C combinations and exactly where you are taking the measurements. If you're really measuring at the Vout pin of the DAC rather than measuring the output of the op amp it makes good sense that you cannot observe any difference from one amplifier to the next. The BW makes a difference. This architecture of DAC does not have an on-silicon buffer like many of our other DACs that you may be used to.

    Martin Hansel said:
    I was not aware, that the plots are showing the behaviour of a circuit but not of the device...

    That's really the only practical and fair way to present device performance on an unbuffered DAC. Without the amplifier isolating the resistor string from a load impedance you would get poor results.

  • Hi Kevin,

    my changes/workarounds aren't yet drawn in a schematic - I'm still trying...

    But, as described earlier: 47p just from Vout (Pin2) to GND.

    And, I'm not talking about the difference from "one amplifier to the next", but about the response of my "system_under_test".

    This is a bit more complex:

    Mainly a TIA (OPA129), but voltage-commanded by one DAC (and buffer for sure...). Very high Gain (2nA/V) and bandwidth FAR BELOW the glitch (1..10kHz).

    The impedance to be measured is resistive, but overlayed by a (huge) parasitic capacitance.

    Normally, the effect of the capacitance (known value) is digitally compensated "ahead", by a second DAC. (That's one of the reasons, why I need an update-rate >1MSPS)

    Maximum rise-time of the signals should be <5us, so I'm limited with RC-filtering.

    And, even when varying the filter-constant, the response of my system only varies slightly.

    Practical and fair: Everybody knows (or should know) how to handle an unbuffered voltage dac. But by showing only the output of an Op-Amp (btw: which one was used?) veils the original waveform.

    Rgds

    Martin


    CPS-Amp_1.01_SCH-BPlan_Grundversion_auszug.pdf
  • Hi Martin,

    I understand the confusion. The electrical characteristics table are our guaranteed specs which show the amount of glitch energy to expect from the unbuffered output of the DAC. This is the number to go by. The characterization plots shown in the data sheet are showing behavior of one device at one temperature (room temp), you can think of them as typical specs. Characterizing the device, we thought more from a system level in which we used a buffer amplifier for the glitch plot. I believe we used an amplifier with about a 2MHz GBW and I am pretty sure it was the OPA735. We felt that including a glitch amplitude plot at the unbuffered DAC output was not very useful since every application will call for a buffer amplifier at the output. Additionally, as you switch from silicon to silicon, and differences may slightly shape the glitch seen at the unbuffered output differently. The bandwidth of the buffer amp as well as the load on the output of the buffer amp is going to shape the glitch response.

    Regards,

    Tony Calabria

  • Hi Toni,

    thanks for your explanation.

    To make a long story short:

    My primary concern was, if something went wrong in my circuit. But, as far as I can see now, it seems very probable, that the observed waveform (250mV/400ns), will be seen at the Vout-Pin of the unbuffered DAC. Can you confirm this ?

    So now its up to me, to find a suitable solution:

    -- filtering the signal

    -- addional T/H-circuit

    -- changing the DAC

    Regards,

    Martin

  • Hi Martin,

    In my experience, the track and hold circuit solution is not necessarily the easiest thing to implement. Kevin suggested changing the op amp to one of slower bandwidth which would help with the amplitude of the glitch for the trade off of settling time. If settling time is a concern, then the solution of changing the op amp or RC at the output would not work. Your first post mentions that you are implementing the DAC into a high speed control loop application. I am not sure exactly what your settling time target is but the DAC8562 may fit. This DAC has an internal output buffer and very low glitch (due to its string DAC topology versus the DAC8832 R2R design). Settling time we spec is on the order of 7-10us but keep in mind that the spec is for a 1/4 - 3/4 scale step. That settling time is including the time for the output voltage to slew as well, which would be much less if you are doing small voltage steps. This part may fit otherwise.

    Regards,

    Tony Calabria

  • Hi Toni,

    thanks for your suggestions.

    A home-brewn T/H will be the last option for me. R/C and OPAMP will not work in my application, so I'm look for an alternative DAC.

    Settling time is not my biggest concern, about 5us would be ok.

    The DAC8562 has a very nice glitch-spec, but have you ever looked at that horrible LDAC-feedthrough ?

    One of your competitors is offering a VERY SIMILAR DAC, but with much better glitch-specs...

    Rgds

    Martin

  • Hi Martin, 

    Digital feedthrough being 100pV/s also is going to change its visual appearance depending on the output load. Any capacitance on the output of the DAC8562 is going to attenuate the digital feedthrough amplitude and you should be able to have it settle out well within 5us while attenuating the amplitude quite a bit. Are you comparing the digital feedthrough 0.1nV/s number to the competitor or looking at the figures to see what the amplitude looks like? Reason I ask is the amplitude is going to change with output load so the digital feedthrough visual representation from our competitor to us may change due to the test conditions rather than the parts performance.

    Regards,

    Tony Calabria

  • Hi Toni,

    digital feedthrough is very high-frequent generally (in may case sclk=38MHz), more or less symmetrical, so it can (and will be) filtered out quite easily.

    But I wasn't talking about "digital-feedthrough" when comparing to your competitor but about the "major-carry-glitch" compared to the DAC8832.

    Here your specs are: 35nV-s   Competitor: 1.1nV-s

    Typical Values:

    DAC8832: 250mV for 400ns   (measured by me at DAC-Output, unloaded) estimated energy: 0.25mV x 400ns / 2 == 50nV-s -- not so far from the specs...

    DAC8832: 30mV for 1.5us (estimated from Figure 20 in DS, measured after OP) : 0.03 x 1500ns / 2 =22.5nV-s -- also very near to your Spec

    Competitor: 8mv for 100ns  + 1mV for 200ns = 0.8nV-s + 0.2nV-s = 1.0 nV-s -- near to the specs

    So I'm expecting an improvement of at least factor 10

    Rgds and a nice weekend

    Martin