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ADC THS1007

RAJAT GUPTA
Prodigy 95 points
Other Parts Discussed in Thread: THS1007, THS10064

Sir, 

        Can I use this (THS1007)ADC's channel input as within the range of 0-3.3V by using Vrefm=0V and Vrefp=3.3V.

        Another quesion is, do I have to change my CS0, CS1 and RD input of ADC at each conversion for retreiving the digital output from it.

        Actually I am worried about READ signal that has been shown in the timing diagram wihtin the datasheet.   How can they generate this READ signal with nearly same frequency of CONV_CLK.?

    Do have to pass rd = conv_clk or something else?

  Please provide your answer as soon as possible.

  • 0
    TI__Guru**** 173636 points

    Rajat,

    The THS1007 is designed to have a 2V input swing, with VREFM at 1.5V and VREFP at 3.5V.  The minimum voltage on VREFM is 1.4V, so trying to tie that node to GND (0V) is not recommended.  The THS1007 is also generally used with an FPGA or state machine type controller - if you are using a DSP or micro controller to interface with the device, I suggest that you consider using the THS10064 instead.  The CS0 and CS1 signal can be held static.  RD must toggle for every conversion result.

  • 0 in reply to Tom Hendrick
    Prodigy 95 points

    Sir, 

            But in datasheet they have said that there is an extra feature for external Vref , what does it mean ??

           And I am working with FPGA Nexys-2 Board . Now problem that's occuring is I am getting digital output at D0-D9 but I don't get any signal at SYNC from IC , since I am using it at multichannrl mode.

    Please provide your answer.

  • 0 in reply to RAJAT GUPTA
    TI__Guru**** 173636 points

    Rajat,

    Yes, the data sheet tells you that it is possible to use an external reference source, but there are limitations:

    The minimum VREFM is 1.4V and the maximum VREFP is AVDD - 1.2V - the difference between the two should be 2.0V which is the maximum input range of the device.

    The THS1007 is a pipeline converter and there is a delay of 7 + the number of sampled channels before you will see it become active.  Assuming you have four SE inputs, this means is that you have to have 11 CONV_CLKs before you see SYNC toggle low.  You don't want to read data before you see the SYNC, otherwise you will never get that signal to toggle.  You have to reset then configure the device first, toggle CONV_CLK  11 times and then you should see the SYNC start acting like the wave form depicted in Figure 31.  Once SYNC toggles low, you need to toggle RD with every CONV_CLK to maintain the correct synchronization.  The THS10064 uses DATA_AV instead of SYNC - this acts more like an interrupt so that you don't need to keep track of the CONV_CLK cycles like you do with the THS1007.

  • 0 in reply to Tom Hendrick
    Prodigy 95 points

    Sir, 

           As you have said that i don't want to read data before I see the SYNC, and I have to configure first  and wait for CONV_CLK to toggle 11 times so the question that is running in my mind is, after configuring the IC when will I change the value of wr pin from 0 to 1, since now I dont have to write any data in for configuring.

       Do i just change the value of WR pin after configuring the IC or I have to wait for some clock cycles?

      Please solve the remedy ?

  • 0 in reply to RAJAT GUPTA
    TI__Guru**** 173636 points

    Writes to the THS1007 do not depend on the conversion clock.  The /WR and /RD signals are active low, so they should be brought high when you power up the system.  The /WR pin has to be toggled low and then returned high when you write to the CR0/1 registers.

  • 0 in reply to Tom Hendrick
    Prodigy 95 points

    Sir,

          According to your previous reply , are u suggesting me that when I have to write data into IC then I have to make wr pin =1.???

       Its bit confusing sir.

  • 0 in reply to RAJAT GUPTA
    TI__Guru**** 173636 points

    Please review Figure 34 and Figure 35 in the THS1007 data sheet.  These assume the /WR pin is configured as RD/WR (bit 6 in CR1 is set, refer to Table 11).  Please also refer to Figures 40 and 41 in the THS10064 data sheet.  Those two figures apply to the THS1007 as well when bit 6 in CR1 is cleared.