Hello.
ADC16DV160 has maximum Conversion Rate and Input Clock Frequency (FCLK) of 160 Msps/MHz. In case when clock divider (/2) is enabled, does the FCLK maximum become 320 MHz, thus maintaining maximum Conversion Rate of 160 Msps, or stay unchanged from 160 MHz so maximum conversion rate available is 80 Msps?
Kind regards, Ivan.
