• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 47 subscribers
  • Views 619 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE5801 clocking

John Lee2
Prodigy 60 points
Other Parts Discussed in Thread: AFE5801, AFE5808, LMK00306, LMK00304, LMK00301, LMK00308, LMK01801, LMK00101, LMK00105

Hello,

When producing clocks (for ADC) for AFE5801, do you see any issue with using FPGA to create the clock? I am using Xilinx Spartan-3. The FPGA uses clocks from a PLL (CY68013A), however, I am not sure what the jitter is like if I FPGA uses that clock to generate another clock. I know this is hard to answer without me providing any real values (jitter, etc.) but I am looking for some intuitions from the ultrasound experts...

The evaluation board uses another chip to create the clock, but I was hoping if I can synchronize the clock with my "system" clock so that I can control easily when to turn on/off AFE ADC clock as well as control number of cycles and such. This is pretty trivial if I use the FPGA, but not sure if ADC performance will be degraded too much.

Thanks in advance for the help!

John

  • 0
    Intellectual 710 points

    Hi John,

    Yes, you can create the clock using FPGA, however it is strongly recommended to distribute it to the multi-AFE system through the fan-out buffer.

    Read more about it here:

    http://www.ti.com/ww/en/analog/clockdrivers/

    Good luck..

  • 0 in reply to Mariusz Hajduk1
    Prodigy 60 points

    Hi Mariusz,

    Thanks for the answer. So just to double check,I am talking about producing the ADC clock using an always block (in verilog) off of a system clock that is coming from an external PLL and using a regular pad (CMOS single-ended)

    I am using only single AFE chip (8-channel system)... do I still need a clock buffer?

    Thanks!
    John 

  • 0 in reply to John Lee2
    Intellectual 710 points

    Hi John,

    It depends what  the max clock frequencies. It's always less risky to use differential clock source then single-ended. Therefore I recommend to buffer the single ended clock from the FPGA converting it into differential. Also, I recommend to change your design as follows:

      Choose a stable clock generator, connect it's output into the buffer and then distribute the separate clock lines into AFE, FPGA and whatever else you need.

    In my designs 32/64 systems it works fine. As a clock distribution chip I use AD9512.

    Good luck!!

  • 0 in reply to John Lee2
    Intellectual 710 points

    Hi John,

    One more suggestion, take a look at AFE5808 pdf (Fig.90 on page 59). This should be the best answer for your question.

    Regards.

  • 0 in reply to Mariusz Hajduk1
    Prodigy 60 points

    Hi Mariusz,

    Thank you for your suggestions! I really appreciate your help. It sounds like the second idea (from AFE5808 datasheet) might work the best for my case. I will give it a try!

    Thanks again!

    John 

  • 0 in reply to John Lee2
    Intellectual 710 points

    Hi John,

    I'm glad that I've helped you somehow. Anyway, the first idea is also approved in practice. Whichever you choose, it should work fine.

    Best Regards,

    Mariusz

  • 0 in reply to John Lee2
    TI__Mastermind 32575 points

    Hi John, Mariusz,

    TI also has some ultra-low-noise clock distribution devices with as low as 30 fs RMS additive phase jitter for Medical Imaging and other High-Speed ADC clock driver applications:

    1. LMK00304, LMK00306, LMK00308, LMK00301: 4/6/8/10-output Diff Clock Fanout with pin-selectable output formats (LVPECL, LVDS, HCSL) and 3:1 Input Mux
    2. LMK01801: Dual Channel Clock Divider/Buffer with up to 14 DIFF outputs, pin-selectable or SPI-programmable channel divider and output formats
    3. LMK00105, LMK00101: 5/10-output 1.5-3.3V LVCMOS Clock Fanout with Input Mux

    Regards,
    Alan