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ADC16DV160 Latency

Ryan McCourt
Prodigy 130 points
Other Parts Discussed in Thread: ADC16DV160

I'm trying to understand the ADC latency on the ADC16DV160, and have a few questions.

We're using them in a system where we have multiple ADC16DV160 chips on the board, all synchronized to the same clock. The datasheet specifies a typical latency of 11.5 clocks, but when I look at the timing diagram (Figure 3), the latency isn't defined in a way that relates it to the output clock.

Questions:

- With multiple ADC16DV160 chips running on the same board (same temperature, same clock source), will there be any difference in the latency through the different chips?

- Is there a defined relationship between CLK and OUTCLK?

Thanks for any information you can provide -

     -Ryan

  • 0
    TI__Expert 4340 points

    Hi Ryan,

    The latency (coarsely described) in units of clock cycles is 11.5 cycles. The fractional 0.5 cycle is due to the sampling instant occuring on the falling edge of input clock whereas the first bits of the output data come out of the digital interface shortly after the rising edge of the input clock with some propogration delay resulting in skew between the input and output clocks. A more accurate way of describing the latency would also include the skew between the input clock and OUTCLK. It might also account for a ~90 degree phase shift of the OUTCLK which was done to align the clock edges in the center of the data eye. The skew between the input clock and OUTCLK was not characterized but will vary slightly with conditions. I estimate that the typical skew is less than 0.5 clock cycles and the skew varies by less than +/-0.25 clock cycles.

    An additional note: When using the internal divide-by-2 clock divider, the initial phase state of the sampling clock relative to the input clock is unknown. If this is a concern, the sampling edge must also be manipulated (in the SPI registers) to synchronize multiple devices.

    Regards, Josh

  • 0 in reply to Joshua Carnes
    TI__Expert 4340 points

    As far as sychronizing multiple devices, the latency through the ADC should not change except for the input clock to OUTCLK skew. That skew should be similar between multiple parts so you should be able to synchronize multiple parts.

    Josh