Other Parts Discussed in Thread: ADS8028, ADS7886
Hi,
In one of my designs I am using an ADS8028 ADC. It is being clocked at 12MHz. 6 of the 8 channels are being used and the internal temperature sensing is not being used.
The 6 inputs are being fed by a ACS758-150B hall-effect sensor with a 10R-1nnF output low-pass filter.
This exact same arrangement has been done by us in the past using discrete ADC's (ADS7886) without any problems
The ADS8028 was chosen due to pinout restrictions on our main FPGA resulting in a multichannel ADC being the only option to proceed with.
The DVDD is powered from a 3v3 rail, the AVDD is powered from a 5V rail (both a derived from a 6.2V rail via LDO regulators). The REF pin is pulled upto 5V via a 1k2 resistor (to limit the current that the REF pin sinks before the ADC is configured to use the external reference). The external reference is being pulled to 5V to provide ratiometric gain with respect to any 5V rail variation since the HallEffect sensors also have ratiometric gain.
The FPGA requests each of the 6 channels sequentially (we originally configured it with a control work 0xFF04 for continuous sampling,external reference but found some integration issues with this).
The problem I am seeing is on the converted data. Viewing the sampled data from the FPGA it seems like the data is jumping in steps of 8decimal as oppose to 1decimal. Considering this is a 12bit ADC (and thus 4095 being the maximum) this is quite concerning. Also there didn't seem to be much analogue-induced LSB toggling, something I expected to see due to random noise.
removing all the R's from the R-C filters on the 6 inputs and connecting all the inputs together to a precision voltage source which can be control in 1mV steps (5V/4095 == 1.2mV per LSB) as well as monitoring the nCS, CLK, DOUT pins of the ADC, I was hoping to see the Least significant bit toggling at all levels, again due to noise. I however am not seeing this.
Injecting 0V into the ADC while monitoring on an oscilloscope the nCS,CLK,DOUT (and interogating the controller), I can see the LSB and other lower bits toggling.
This is mirrored in the controller data which shows channels giving decimal readings of {0,1,2} {2,3,4,5} {4,5,6,7,8} etc (ie some analogue noise toggling the bits. My aim was to increase the input in 1mV steps at a reasonable rate and I hoped to see the binary stream have a classical ripple effect.
What I see however is once the input voltage reaches ~0.5V the least significant bit no longer toggles all the way upto 5V input.
just above 0.5V the "analogue noise" jitter on the data rather than jumping 1lsb starts to toggle at 2lsb ...
Increase the input voltage further until around 1.5V and more and more lower order bits stay at "1" and the decimation steps increases until the steps are at 8decimal - ie the lower 3 bits stop toggling, something I would expect to occur even in the presence of analogue noise or with an input signal increasing in 1mV steps to 4.900V
A so called 12bit ADC is starting to appear as a 9bit ADC for inputs above 1.5V but the lower bits stuck at 1. I can decrease the input voltage and the lower bits start to toggle as expected.
Any idea or information why an ADC which from the datasheet seems to be a 12bit ADC, would start to be have as a 9bit ADC with the lower bits stuck at 1
Jonathan Roadley-Battin - Principal Engineer - Motor Drives Systems
UTC AEROSPACE SYSTEMS
