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Load capacitance on LVDS outputs of ADS5444-SP

Mike Thielman
Prodigy 80 points

Is there a recommended or maximum allowed load capacitance on these outputs in order to ensure device performance?  We have a situation where we wish to have an ADC and the FPGA it connects to on separate boards, connected via a coax ribbon cable.  Could the ADC drive this directly, or must a buffer be used?  The ribbon cable is 50 ohm coax (Samtec HQCD series).  I have seen other data sheets explicitly call out load capacitance requirements (such as stay under 8pF) but nothing on this one.

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    TI__Expert 4420 points

    MIke, older devices might not have all the information as the newer ones. After talking to people who have worked with this device longer, looks like the characterization data might have been taken using C=10pF. However, this number should not be used as a specification. I can tell you however, that in general, buffers should be avoided since they could introduce additional skew among other issues. Also, for LVDS, the capacitive load that would affect the signal would be the one closer to the source of the LVDS signal, in this case the ADC. Loads far enough down the transmission line that the driver doesn't see will just present reflections, which by the way a buffer wouldn't make go away anyways.

    Hope this helps,

    JV