Hi,
There are some issues regarding the SPI data comunication on ADS1246/7/8. Datasheet is not clear about the number of CLKs needed with some commands:
SYNC - 16 CLKs with CS low or 2 x 8 CLKs with CS low on each byte (Figure 74)?
RREG - 16 CLKs with CS low or 2 x 8 CLKs with CS low on each byte/command? Also, the register read cycle (Figure 80) also need 16 CLKs?
WREG - There must be one frame only with 24 CLKs (figure 80) or two frames after the command has been issued?
Regards,
MC